Hadi-Alik
Member level 4
system generator ce vhdl
Hi Guys
I'm a beginner in FPGA, but I used Xilinx System Generator to produce VHDL files successfully. Then I used the files in ISE to program my Spartan-3E board. But, the when I open constraint file to edit it, I see some strange port names:
which are the port name introduced in the first entity of the VHDL file, while the correct port names I need are placed in the middle of the VHDL file:
Any idea why It happens like this? is it a system generator bug? the file is very big (3600 lines) and I can not manage it by hand!
Cheers
Hadi
Hi Guys
I'm a beginner in FPGA, but I used Xilinx System Generator to produce VHDL files successfully. Then I used the files in ISE to program my Spartan-3E board. But, the when I open constraint file to edit it, I see some strange port names:
Code:
clk
clr
ce
fakeOutForXstwhich are the port name introduced in the first entity of the VHDL file, while the correct port names I need are placed in the middle of the VHDL file:
Code:
active_high_shutdown_reset
ce
clk
clock
from_dce_for_voltage_mult
miso: in std_logic
to_dce_for_observationAny idea why It happens like this? is it a system generator bug? the file is very big (3600 lines) and I can not manage it by hand!
Cheers
Hadi
