dpaul
Advanced Member level 5
Xilinx MIG Traffic Generator problem
Hello,
I am trying to debug a problem for our MIG. Part nos is xc7a100t_1 + Vivado 2015.4.
(For an older ver of Vivado (probably 2014.x) with older versions of the IPs the design was working with the above FPGA part nos at the board level. Unfortunately the engineer who had worked on this is now not available. Then the Viv s/w was upgraded to 2015.4 and the Xilinx IPs were automatically upgraded).
Now we have same board, with the same FPGA and the same 4GB DDR3 memory chips. But Viv is now 2015.4. Using the exact configurations, no problem is seen at the simulation level. When the same example design (containing the MIG & Traffic_gen) is bit-streamed into the above FPGA on the board, memory Initialization and Calibration completes successfully. The problem is seen during compare data stage. Basically there is no valid data to compare with the read back data!
When I set the ILA trigger dbg_cmp_data_valid == 1, and then run, the trigger waits for ever. This is because this signal never becomes HIGH. I see the 64 bit dbg_cmp_data_r to be always 0s. One can also see that dbg_tg_compare_error is always LOW from the beginning.
However dbg_rddata_r always has valid data (indicating that data is being read back from the on board DDRs). Please see the attached screenshot.
I guess there is a problem in the traffic generator engine.
Has anyone worked with a similar problem? How can I go for debugging the the traffic gen?
Hello,
I am trying to debug a problem for our MIG. Part nos is xc7a100t_1 + Vivado 2015.4.
(For an older ver of Vivado (probably 2014.x) with older versions of the IPs the design was working with the above FPGA part nos at the board level. Unfortunately the engineer who had worked on this is now not available. Then the Viv s/w was upgraded to 2015.4 and the Xilinx IPs were automatically upgraded).
Now we have same board, with the same FPGA and the same 4GB DDR3 memory chips. But Viv is now 2015.4. Using the exact configurations, no problem is seen at the simulation level. When the same example design (containing the MIG & Traffic_gen) is bit-streamed into the above FPGA on the board, memory Initialization and Calibration completes successfully. The problem is seen during compare data stage. Basically there is no valid data to compare with the read back data!
When I set the ILA trigger dbg_cmp_data_valid == 1, and then run, the trigger waits for ever. This is because this signal never becomes HIGH. I see the 64 bit dbg_cmp_data_r to be always 0s. One can also see that dbg_tg_compare_error is always LOW from the beginning.
However dbg_rddata_r always has valid data (indicating that data is being read back from the on board DDRs). Please see the attached screenshot.
I guess there is a problem in the traffic generator engine.
Has anyone worked with a similar problem? How can I go for debugging the the traffic gen?
