siddharthakala
Member level 2
A few days back I got a warning on Xilinx ISE after synthesizing a design which said something like - Certain features are only available in SystemVerilog mode. Since then I have been trying to see how to activate this "SystemVerilog mode" but didnt get a clue about it. Does anyone know if there is any such feature that allows you to use SystemVerilog for writing synthesizable code in Xilinx ISE?
I am using Xilinx ISE 13.2.
Is there any other synthesis tools that support SystemVerilog for synthesis. I have Synplify but it doesnt support SV as well.
I am using Xilinx ISE 13.2.
Is there any other synthesis tools that support SystemVerilog for synthesis. I have Synplify but it doesnt support SV as well.