Xilinx FPGA FIFO core

[yanqele]

Newcomer.
Can somebody please answer two simple questions? I could not find the answer in docs.

The configuration submitted to CoreGen is the most simple one, all defaults, except I need a width of 32 bits and a depth of 4096.

The header generated by CoreGen (VHO file) specifies one input named clk to the core.
Do I have to program that clock? Is it not possible to simply use the 50MHz system clock? And then, how do I connect the system clock to the clk signal? Just a simple permanent assignment (that is, not in a process) ?

Other question: how do I configure with_parity/without_parity? Is parity automatically added to the stated width, or included in the stated width, and then who manages the
parity bit, one per byte I guess, is it automatic or do I have to progam it myself?

Thanks in advance

 

[ombadei]

I have used the coregen fifo quite some time back.... lets see if i can answer you..

The header generated by CoreGen (VHO file) specifies one input named clk to the core.
Do I have to program that clock? Is it not possible to simply use the 50MHz system clock? And then, how do I connect the system clock to the clk signal? Just a simple permanent assignment (that is, not in a process) ?

Once you generated the fifo through the wizard setup(VHO file).. all you have to do is to treat it like a component.. Instantiate it and declare signals to map it.. then follow the datasheet on the specific timing operations.. i.e you can use whatever clock you like..

Although if you find it too confusing, write you own FIFO.. at least you will be better aware..

Other question: how do I configure with_parity/without_parity? Is parity automatically added to the stated width, or included in the stated width, and then who manages the
parity bit, one per byte I guess, is it automatic or do I have to progam it myself?

Dun remember about parity checking for the coregen fifo.. but honestly.. not sure whether its feasible for parity checking.. unless ur datapath is really complex(?!) after synthesis.. seems to me that u hv to program it yourself if you really want it and add the required parity bit..

 

[yanqele]

Thanks for answering.
I am a physicist. As such I always try to avoid reinventing the wheel.
I asked about how to suppress parity because the default FIFO core parametrization yielded an error message for a dangling bit : the parity is thus implemeted (v 4.4).
Likewise I asked how to make the clock because I desperately looked for an example.
I know how to make a clock, I made one to drive an RS232 port; the question is, which clock to design.
Anyway, thanks again for your answers, they did raise some light.

Yanqele

 

[rberek]

If you used FIFO Generator in Coregen, it does not add parity, at least for Virtex 5 and Virtex-6. It will add ECC, but only if you tell it to, its not the default.

Because all FIFO's are made from 18 bit-wide memories, your FIFO will be 36 bits wide, and you can use the 4 extra bits for parity or whatever you want. If you want parity, you will have to write parity generation and checking code yourself.

r.b.

 

[yanqele]

I am using a Spartan 3AN development board (Digilent sold by Xilinx).
The board has a 32Mx16 bits DDR2 RAM and indeed I see no room for parity on this hardware interface.
I understand, am I wrong?, that the Core FIFO generator automatically selects this RAM.
My worry and my question came after synthesizing and implementing a test design: I got a Warning messgage for a dangling parity bit.

Thank you very much for your enlightening and assertive answer.
I will now just ignore this warning message, hoping for the best.

Yanqele

 

[rberek]

I'm not exactly sure what you mean, but it sounds like you are trying to use an external memory as a FIFO.

The core generator builds FIFOs out of the internal rams in the Xilinx part. It knows nothing about any external memories, and would not build a FIFO with them even if it did.

If you want to use an external memory, you will have to design a memory interface for it, or use Coregen to build a DDR2 Memory interface, using the Memory Interface Generator, not the Core Generator.

I notice that Coregen has lionks to a 200MHz DDR2 memory controller reference design too.

However, if you wish to use the DDR2 SDRAM as a FIFO, I think you'll have to write the code yourself.

r.b.

 

[yanqele]

Sorry, I made an inattention mistake when I wrote my last mail.

I want to build my FIFO using 64kbits out of the 360kbits Block RAM available in my FPGA. Nothing to do with the DDRAM on the development board.
Do I correctly understand that I just need to create a clock derived from the system clock and an FSM to store and later fetch my data?
Why should I need an 18 bits width when my data is just 16?

Thank you very muh for your help and your patience.

Yanqele

 

[rberek]

Yes, that's all you have to do.

Regarding memory width, I was only pointing out that in some (possibly all) of Xilinx's families, the memories are of fixed width. In Virtex-5, the width is 18 bits. so even if you only want 32 bits, you'll get a 36-bit wide memory because it will stick 2 18-bit block rams together.

r.b.

 

[yanqele]

Thanks again.
I begin to understand and as I progress I do find the documentation, unfortunately spread in many places - not easy for somebody who sees that for the first time...

May I ask one hopefully last question?
I configured the core for a BRAM buffer of width 36 and depth 4096 .

The ISE Device Utilisation Summary reports under Number of RAMB 16BWEs :
Used 1, available 20, Utilization 5%.
The utilization figure matches my Spartan 3AN FPGA which indeed has 360kbits of BRAM since one block has 18 kbits (incl. 2 for parity).

But I expected my buffer definition to need 8 such blocks, not 1.

Could it be that the ISE software is clever enough to find that although I requested
144kbits my actual code for this training test uses only 288 bits, thus needs no more than one RAMB-16BWE ?
Or should I suspect a bad generation of the core?

Best regards
Yanqele

 

[rberek]

Depending on how you wrote your code, ISE may have decided not to route all of the BRAMs in your core. As a test, change your RTL to use mroe fo the memory and see if ISE uses more of the blocks.

r.b.

 

[yanqele]

Re: Xilinx FPGA FIFO core = SOLVED, Thanks to rberek

Dear Rberek
Many many thanks for having rescued me!
The short test and the final application (1100 lines of vhdl code) worked fine immediately. Easier than I can say once understood.
And yes ISE knows how much BRAM to take. It does use the expected 8 blocks.
Wonderful tool.

Congratulations for your guidance - from a 75 years old university Physics prof moderately experienced with FPGA's and VHDL, but with 40 years of scientific computing in more than 25 languages including at least 10 assemblers...

-------------------

Thanks again.
I begin to understand and as I progress I do find the documentation, unfortunately spread in many places - not easy for somebody who sees that for the first time...

May I ask one hopefully last question?
I configured the core for a BRAM buffer of width 36 and depth 4096 .

The ISE Device Utilisation Summary reports under Number of RAMB 16BWEs :
Used 1, available 20, Utilization 5%.
The utilization figure matches my Spartan 3AN FPGA which indeed has 360kbits of BRAM since one block has 18 kbits (incl. 2 for parity).

But I expected my buffer definition to need 8 such blocks, not 1.

Could it be that the ISE software is clever enough to find that although I requested
144kbits my actual code for this training test uses only 288 bits, thus needs no more than one RAMB-16BWE ?
Or should I suspect a bad generation of the core?

Best regards
Yanqele

 

[rberek]

No problem!

I'm glad it worked out for you.

r.b.

 

[Umair_ali]

I use Altera's Mega wizard to create FIFO buffers and RAMs..... You need not to worry about the frequency...... however you can synthesize your final design and get fmax, the maximum frefuency on which you can run your design.... after that you can select any frequency below the fmax.... and your design will run Fine

Also you dont need the internal code of FIFO.... If you Know how a FIFO behaves... all you need is write a testbench and chk your result..... while simulating your design... you should provide a file other than .v (its Alter_mf) to the simulator so that it can understand what the X-code says.