unix_amr
Junior Member level 1
Dear researchers and students;
I am trying to implement an SRAM in HSPICE by TSMC65nm technology. The restrictions on both width and length in this PDK are as follows:
Lmax= 2.401E-07
Lmin= 6.000E-08
Wmax= 6.010E-06
Wmin= 6.000E-07
In your opinions, is there any way to define a MOS with width of 300nm? it is obvious that modifying PDK is not recommended.
Any help is appreciated.
Regards,
I am trying to implement an SRAM in HSPICE by TSMC65nm technology. The restrictions on both width and length in this PDK are as follows:
Lmax= 2.401E-07
Lmin= 6.000E-08
Wmax= 6.010E-06
Wmin= 6.000E-07
In your opinions, is there any way to define a MOS with width of 300nm? it is obvious that modifying PDK is not recommended.
Any help is appreciated.
Regards,