wmin and wmax ranges

[unix_amr]

Dear researchers and students;

I am trying to implement an SRAM in HSPICE by TSMC65nm technology. The restrictions on both width and length in this PDK are as follows:

Lmax= 2.401E-07
Lmin= 6.000E-08
Wmax= 6.010E-06
Wmin= 6.000E-07

In your opinions, is there any way to define a MOS with width of 300nm? it is obvious that modifying PDK is not recommended.

Any help is appreciated.
Regards,

 

[dick_freebird]

If the flow allows "dog-bone" FETs then you can get
a W less than the (contact + AA oversize of contact)
that an ortho FET would require. What is min AA width?
You won't get below that in any case.

Wmin is usually lithography, Wmax (M aside) may
be either tap rules or the modeling guys saying
"can we quit now?" re the geometry-space they
have to cover.