shaq
Full Member level 5
Dear all,
I have a little question that is why we usually set ac=1v during simulate such as dc gain, phase margin and ugbw.
Just like this.
I have a little question that is why we usually set ac=1v during simulate such as dc gain, phase margin and ugbw.
Just like this.
Code:
vin vin gnd dc 'vdd*0.5'
vip vip gnd dc 'vdd*0.5' ac 1.0
.ac dec 10 1Hz 1GHz
.probe ac vdb(vout) vp(vout)