why the DFT test_clock ;s duty cycle is 10%,not 50%?

[nine8]

in DFT,

the test_clock period is 100ns , and duty cycle -timing {45 55}, why not {0 50} ?

 

[jaydip]

I have done DFT with 50% duty cycle only .. Did you read this in any standard, it should be 10%?

 

[vlsi_eda_guy]

you can not have it as {0 50 } , beacause the PI has to be forced from Tester before the clock can come. Again you have to give some time for the PI to settle before you can give the clock. If not you will get setup violations....

Also, if you are doing pre-clock strobe then you will give time for the storbe as well... The default for the strobe is 40 .


Always keep in mind the tester are cyclic in nature..... All the events have to happen at the same time in all the cycles.

-cheers
vlsi_eda_guy