[SOLVED] Why some modules don't appear in the Netlist after synthesis using Vivado 2019.1

[MSAKARIM]

In my code i have around 6 sub-modules, 2 of them(&their inputs and outputs) only appear in the Netlist. the other 4 modules don't appear completely, also utilizaion table in the project summary seems that it is affected by this. Although when i tried to see the RTL Schrmatic of the top module all sub-modules appear!!
the code seems to be okay has no errors.

 

[FvM]

Not clear what "don't appear completely" means. However logic that has no actual function because no design output depends on is discarded during synthesis.

 

[MSAKARIM]

Not clear what "don't appear completely" means. However logic that has no actual function because no design output depends on is discarded during synthesis.

they has actual function,
i want to know, what are the reasons of disappearing some of sub-modules in the netlist?

 

[FvM]

What do you see if you trace an output of the respective module in the net list?

 

[ads-ee]

Occasionally when the synthesis tool determines that an output is statically 0 or 1 and is connected to something in another level it will propagate the constant output value and remove all the logic driving that output. Have you verified that isn't the case?

If you are worried about it then run a functional netlist simulation using the same HDL functional simulation you used to verify the design. Depending on how well you simulated the HDL code that might prove or disprove that something important was removed.

 

[MarkPh]

In my code i have around 6 sub-modules, 2 of them(&their inputs and outputs) only appear in the Netlist. the other 4 modules don't appear completely, also utilizaion table in the project summary seems that it is affected by this. Although when i tried to see the RTL Schrmatic of the top module all sub-modules appear!!
the code seems to be okay has no errors.

Look at KEEP_HIERARCHY
e.g. http://www.xilinx.com/support/answers/54778.html

 

[MSAKARIM]

It is solved.
I used " attribute dont_touch " to prevent optimization in https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug901-vivado-synthesis.pdf page 38