Why PLL is stable with positive gain margin?

[pulkit shah]

AT DC and lower frquency, PLL has positive gain margin. Why PLL is stable with positive gain margin.

 

[tuki]

PLL stability

Why you say positive gain margin? If the system is stable or unstable , you must see open loop gain
phase margin !!! Can you say more detail ?

Added after 2 minutes:

sorry !!! I can see the paper
**broken link removed**

 

[eng_Semi]

Re: PLL stability

The PLL can't have a +ve PM at low frequencies, check it again

 

[pulkit shah]

Re: PLL stability

PM is fine. It has to be 45 degree for stability. But we should have3 negative phase margin for any feedback system. I am talking about open loop respons. AT DC we have two poles in third order PLL. One is from VCO which is 1/s and another is from chrge pump.

 

[pulkit shah]

Re: PLL stability

I mean, PLL has 45 degree PM. But Gain margin is very high. We always expect -6DB GM in feedback system.