why output didnt get the value of signal in last clk?

[fahim1]

hi heres my code and the value o fignal is calculated correctly but at the ninth clk when the calculation finished ,out put should get the value but it didnt happen?
how could i fix it??
tnx

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
entity serialnew is
port(a,b : in std_logic_vector(3 downto 0);   ---b delete
  clk : in std_logic;
  out3 : out std_logic_vector(7 downto 0));
end serialnew;
architecture serialnew_arch of serialnew is
  signal count :integer range 0 to 9 := 0 ;
  signal c0,c1,c2,c3 : std_logic := '0' ;  
  BEGIN
    process(clk)
    variable sum0,sum1,sum2,sum3 : std_logic := '0';
    variable temp0,temp1,temp2,temp3 : std_logic_vector(1 downto 0) :="00";
    variable outtemp : std_logic_vector(7 downto 0) := "00000000";    --?/
    variable inp :std_logic_vector(3 downto 0) := "0000";
    begin
      if (clk='1' and clk'event) then 
        if (count <9) then
          case count is 
       when 1 => inp := b(0) & "000";
       when 2 => inp := b(1 downto 0)&"00";
       when 3 => inp := b(2 downto 0)& "0" ;
       when 4 => inp := b(3 downto 0);
       when 5 => inp := '0'&b(3 downto 1); 
       when 6 => inp := "00"&b(3 downto 2);
       when 7 => inp := "000"&b(3); 
       when others => inp := "0000";
       end case;
        temp0(0) := ( a(0) and inp(3) )xor c0 ;
        temp0(1) := ( a(0) and inp(3) )and c0 ;
        sum0  := temp0(0);
        c0 <= temp0(1);
        ----------------------------------
        temp1(0) := (a(1) and inp(2))xor c1 xor sum0;
        temp1(1) := ((a(1) and inp(2))and sum0) or (sum0 and c1 ) or ((a(1) and inp(2)) and c1) ;
        sum1  := temp1(0);
        c1 <= temp1(1);
        temp2(0) := (a(2) and inp(1))xor c2 xor sum1 ;
        temp2(1) := ((a(2) and inp(1))and sum1) or (sum1 and c2) or ((a(2) and inp(1)) and c2) ;
        sum2  := temp2(0);
        c2 <= temp2(1);
        -----------------------
        temp3(0) := (a(3) and inp(0))xor c3 xor sum2 ;
        temp3(1) := ((a(3) and inp(0))and sum2) or (sum1 and c2) or ((a(3) and inp(0))and c3) ;
        sum3  := temp3(0);
        c3 <= temp3(1);
        --------------------------------------
        outtemp(count ) := sum3;
        count <= count +1 ;
      elsif (count = 9 ) then 
      out3 <= '0' & outtemp(7 downto 1);
    elsif (count = 10 ) then
      out3 <= '0' & outtemp(7 downto 1);
      end if;
      end if;
    end process;
  end serialnew_arch;

 

[TrickyDicky]

count doesnt equal 10 yet - you can see it clearly on the waveform. Out3 will only get a value when count = 10

 

[fahim1]

count doesnt equal 10 yet - you can see it clearly on the waveform. Out3 will only get a value when count = 10

when i run the program it didnt go further than count=8 and it stopped at it.why this happened??how can i fix it?

 

[TrickyDicky]

you probably have the run time set to 800 ps.

 

[fahim1]

you probably have the run time set to 800 ps.

no idont put any time constraints but it dont go after 8 clks,i think its because of the code but i dont know where.

 

[TrickyDicky]

There is no limitation in the code you posted - maybe it's in the testbench? or maybe you didnt set the simulation to run long enough

 

[ads-ee]

100 ps clock period?

I'd like to know how the OP expects this design to run at 10GHz in an FPGA.