why my delta sigma modulator generates werid behavior?

[sapphire]

This is a second-order modulator with feedback structure. From the measurement, it outputs a long series of 1 or 0 once a while, then it returns to normal operation...
Since it's only second-order, so it's supposed not to have stability problem. But what would cause this strange behavior? Attached please find the output's spectrum

Thanks!

-Sapphire

 

[fcfusion]

Plot the integrator's values and check for saturation/overflow. That is generally the cause for these errors.

The stability of ∑Δ does not take integrator saturation in account. The methods used to calculate are purely mathematical and do not account for some of the practical implementation issues. So even a 2nd order ∑Δ can give you problems.


If possible post those signals and the output bitstream so we can check it out.

 

[sapphire]

Thanks for your reply. I have a slightly different chip which is working fine. In that chip, the input and feedback paths have separate sampling circuits, but in this chip the two sampling circuits are combined. So, I am not quite sure whether it's related to the integrator's overflow problem. BTW, it's a switched-capacitor circuit.

In addition, I also grounded the input, but it still shows similar behavior in measurement. Does that make sense? I am guessing there might be something wrong with my testing or PCB.

-Sapphire