Why is My EDA Playground Testbench Exiting after just Two Nanoseconds?

[kvn0smnsn]

With the help of people on this forum, I was able to build a module that takes as input a six-bit (Dividend), and outputs a three-bit (Quotient) that is the result of dividing (Dividend) by 10, and also a four-bit (Remainder) that is the remainder of that division. Then I wanted to test it by dividing every third integer from 0 to 63 by ten, and making sure I got the right result. I also threw in 6'b000001 and 6'b111110. So the two files I entered into EDA Playground are:

module FullAdder( cOut, sum, aOp, bOp, cIn);
  output cOut;
  output sum;
  input  aOp;
  input  bOp;
  input  cIn;

  assign cOut = aOp & bOp | aOp & cIn | bOp & cIn;
  assign sum  = aOp ^ bOp ^ cIn;

endmodule

module Mux #( nmBits = 1)
           ( result, control, hgVal, lwVal);
  output [ nmBits-1:0] result;
  input                control;
  input  [ nmBits-1:0] hgVal;
  input  [ nmBits-1:0] lwVal;

  genvar bt;
  generate
    for (bt = 0; bt < nmBits; bt = bt + 1)
    begin
      assign result[ bt] = control ? hgVal[ bt] : lwVal[ bt];
    end
  endgenerate

endmodule

module AddVector #( nmBits = 1)
                 ( sum, aOp, bOp);
  output [ nmBits  :0] sum;
  input  [ nmBits-1:0] aOp;
  input  [ nmBits-1:0] bOp;
  wire   [ nmBits  :0] carry;

  assign carry[ 0]    = 1'b0;
  assign sum[ nmBits] = carry[ nmBits];

  genvar bt;
  generate
    for (bt = 0; bt < nmBits; bt = bt + 1)
    begin
      FullAdder fa( carry[ bt + 1], sum[ bt], aOp[ bt], carry[ bt]);
    end
  endgenerate

endmodule

module DivByTen( quotient, remainder, dividend);
  output [ 2:0] quotient;
  output [ 3:0] remainder;
  input  [ 5:0] dividend;
  wire   [ 6:0] sum40;
  wire   [ 6:0] sum20;
  wire   [ 5:0] sum10;
  wire   [ 5:0] result40;
  wire   [ 4:0] result20;
  wire   [ 3:0] result10;

  AddVector #(6) av40( sum40, dividend, 6'b011000);   // Subtract 40.
  AddVector #(6) av20( sum20, result40, 6'b101100);   // Subtract 20.
  AddVector #(5) av10( sum10, result20, 5'b10110 );   // Subtract 10.

  // For each mux, pass through the least significant bits of the sum if the
  // most significant bit is high, which indicates the subtraction is positive;
  // otherwise pass through the value before the subtraction.
  Mux #(6) mx40( result40, sum40[ 6], sum40[ 5:0], dividend);
  Mux #(5) mx20( result20, sum20[ 6], sum20[ 4:0], result40[ 4:0]);
  Mux #(4) mx10( result10, sum10[ 5], sum10[ 3:0], result20[ 3:0]);

  assign quotient[ 2] = sum40[ 6];
  assign quotient[ 1] = sum20[ 6];
  assign quotient[ 0] = sum10[ 5];
  assign remainder    = result10;

endmodule

and:

module t_DbtAvMx;
  reg  [ 5:0] dividend;
  wire [ 2:0] quotient;
  wire [ 3:0] remainder;

  DivByTen dbt( quotient, remainder, dividend);

  initial
  begin
    dividend    = 6'b000000;
    #2 dividend = 6'b000001;
    #2 dividend = 6'b000011;
    #2 dividend = 6'b000110;
    #2 dividend = 6'b001001;
    #2 dividend = 6'b001100;
    #2 dividend = 6'b001111;
    #2 dividend = 6'b010010;
    #2 dividend = 6'b010101;
    #2 dividend = 6'b011000;
    #2 dividend = 6'b011011;
    #2 dividend = 6'b011110;
    #2 dividend = 6'b100001;
    #2 dividend = 6'b100100;
    #2 dividend = 6'b100111;
    #2 dividend = 6'b101010;
    #2 dividend = 6'b101101;
    #2 dividend = 6'b110000;
    #2 dividend = 6'b110011;
    #2 dividend = 6'b110110;
    #2 dividend = 6'b111001;
    #2 dividend = 6'b111100;
    #2 dividend = 6'b111110;
    #2 dividend = 6'b111111;
    #2 $finish;
  end

  always @( quotient, remainder)
  begin
    $display
      ( "time: %3t, dvdnd: %d, qtnt: %d, rmndr: %d."
      , $time, dividend, quotient, remainder);
  end

endmodule

My results are:

Chronologic VCS simulator copyright 1991-2021
Contains Synopsys proprietary information.
Compiler version S-2021.09; Runtime version S-2021.09;  Nov 20 13:40 2022
time:   0, dvdnd:  0, qtnt: X, rmndr:  x.
time:   0, dvdnd:  0, qtnt: X, rmndr:  x.
time:   0, dvdnd:  0, qtnt: 0, rmndr:  0.
time:   2, dvdnd:  1, qtnt: 0, rmndr:  1.
time:   2, dvdnd:  1, qtnt: X, rmndr:  1.
time:   2, dvdnd:  1, qtnt: x, rmndr:  x.
$finish called from file "testbench.sv", line 34.
$finish at simulation time                   48
           V C S   S i m u l a t i o n   R e p o r t 
Time: 48 ns
CPU Time:      0.440 seconds;       Data structure size:   0.0Mb
Sun Nov 20 13:40:26 2022
Done

This appears to be running two nanoseconds and then stopping. Why isn't the ($finish) causing it to stop after 24 nanoseconds, since I've got twelve statements before it with a (#2) right before each of them?

 

[FvM]

You have 24 delay statements and the simulation is stopping after 48 ns, as expected. The problem is apparently that DivByTen has constant x output and thus nothing is displayed. Check why this is the case.