why is inductance not considered?

[dazzling_deepika]

y is inductance not considered anywhere in digital design(layout,delay estimation,etc)?

 

[sat]

Good question.

Ideally it should be.

I guess, there might be couple of reasons:

1) Absence of support of 'self-ind' & 'mutual-ind' in SPEF, DSPF netlists which is used in timing analysis.

2) Tool that understands such netlists with self-ind & mutual-ind in timing/delay & noise_induced_delay and signal-cross-coupling and so on.

Now, I'll tell you where we take care of inductance.
From 90nm and below - If I take a look at any DRM [Design Rule Manual] from any foundry [At least TSMC and Chrt] It has new design rules regarding parallel run length and number of bends in a close vicinity on all metal structures.

Routers are aware of these.
DRC verification checks these.

BTW, self & mutual parasitic inductance are extracted in Mixed-Signal and pure Analog designs.

 

[elbadry]

I think that even in Analog designs, Inductance extraction is not common (perhaps inductance extraction tools are expensive). Often, people can do a good job even without inductance extraction. Besides, smulation with inductance is prone to convergence difficulties. Having many of them will make simulation quite cumbersome

 

[rfsystem]

The nature for inductance effects is different to capacitance.

The net interaction is a low complexity problem for capacitance coupling. Only next neigborhood net coupling should be considered. Because of the tall stacking of metal it get more 2.5 dimesional to get the coupling but the scale factor is a M*n issue (n ist the numbers of nets).

The inductive coupling is much more complicated because the return current path is not known in advance so depending on the actual net inductance the coupling could affect much more couplings. In extreme cases of inductive coupling of spike current carrying suppy lines and sensitive analog net an n^2 coupling issue.

The future is similar to cap coupling estimation and counteraction are sensitivity driven coupling estimation and layout design guidelines.