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I wouldn't put in copies of the row data I'd only store the abcd data and replicate in both dimensions. Doing this saves 16x of the RAM and 4x over what you're suggesting.
I'm not sure who you are responding to specifically. We are saying the same thing, but I think you might be saying it better.
If this is done, the design will use one block ram on a xilinx or altera device. Further optimizations will not reduce this -- the smallest design would use approximately 4/5ths as much ram. (the logic resource complexity for both designs is similar)
hi TrickyDicky,can i use state machine for this,defining two true dual port ram and switch between rams,in state one write in first ram and read from second ram (and when sth like counter reached to 4*64) then switch to state 2 which is reading from first ram and writting to the second ram.I was thincking defining the clock for writting 4*x of input clk to extend each pixel to four pixel and then defining the clk of reading 4*x of writtng to extend each row to 4 rows(size of ram is 4*size of rows).i would appreciate if u tell me your opinion about this idea,thanks
I wouldn't put in copies of the row data I'd only store the abcd data and replicate in both dimensions. Doing this saves 16x of the RAM and 4x over what you're suggesting.
thanks for suggesting,as i am new to fpga design that was the first thing cross to my mind and unfortunately its not sufficient. what do u think about the idea i said in the last comment.
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