Why does this vhdl code gives error?

[darktangent]

Below is the code i have written for a shift register... It takes an 4-bit input "D" and a single bit input "SI". And there is a select input K to do different type of shiftings.

But i am only considered with the third part when k= 10.

the Statements go some thing like this..

SO <= data(0);
data <= SI & data(3 downto 1);

the problem is that it puts an X in the data ... and moves shifts it .. why is this happening... here is the code...

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

ENTITY shift_reg4 IS 
PORT (
	D : IN  std_logic_vector( 3 downto 0);
	Q : OUT std_logic_vector( 3 downto 0);
	SI: IN  std_logic;
	SO: OUT std_logic;
	K : IN  std_logic_vector (1 downto 0);
	CLK : IN std_logic
	);
END shift_reg4;

ARCHITECTURE behavioral OF shift_reg4 IS

	SIGNAL data,data2 : std_logic_vector (3 downto 0);
	SIGNAL inpt : std_logic;
	
	BEGIN 
	
	data <= D;
	inpt <= SI;
	
		PROCESS (CLK)
			BEGIN
				
			    IF (CLK'EVENT AND CLK = '1') THEN
			
			   	 IF ( K = "00") THEN
			    
			        	Q <= "0000";
			    	 ELSIF (K = "01") THEN
			    
			    	 SO <= D(3) ; 
			        	Q <= data(2 downto 0) & SI ;
			    
			    	ELSIF (K = "10") THEN
			    
			     	 SO <= data(0);
			     	 data <= SI & data( 3 downto 1);
			     	 
			     	 
			     	 		    
			    	ELSIF (K = "11") THEN
			    
			    	 Q <= D;
			    
			    	END IF;
			   END IF;    
		END PROCESS;
END behavioral;

 

[jducluzeau]

you assigned data twice in your code.
once outside the process
data<=D;

once inside your process for k=10
data <= SI & data( 3 downto 1);

These two assignement are done a the same time that's why you have an X as result.

 

[darktangent]

Actually the other values of K does not matter .. I am just testing it for K = 10.

The statements for data are changed like this

XUUU
XXUU
XXXU
XXXX

 

[jducluzeau]

that 's exactly the case where you have a contention.
Two assignments for data then data goes X.

What is the purpose of D input? initialize data registers?

 

[darktangent]

D is an input to the circuit.. .Its 4-bit. then there is another input SI which should be shifted.. Like if the input D is "0011" and the input SI is "1" then the output Q should be "1001" then "1101" then 1110 and so on.

I have saved the value of D in data so it can be shifted but this code has taken my three days and i am stuck.

 

[jducluzeau]

why do you stored D value in data register? why don't you use directly D as you use SI?
what happens if D changes after clock cycle?
This is a strange shift register.
My understanding is you want to do a parallel load of your shift register through D and after you shift in trhough SI. Am I right?

 

[darktangent]

If i shift D the value of input will change ... which should not be changed... or will not change?

---------- Post added at 14:23 ---------- Previous post was at 14:15 ----------

I tried doing it and it gives error .. saying..

Cannot drive input signal D

 

[jducluzeau]

usualy shift register shift one bit input.

My first mind is either you shift SI,
Either you add an input to enable the load of D in your shift register

 

[darktangent]

couldn't get it ...

You want a load input.. which will load D into the register Data and then start shifting ? This will need an input which will go high once only i think ?

correct?

It will

 

[jducluzeau]

a shift register is a chain of FF where the input of one FF is connected to the output of the previous one.
It means there is one bit input for shift-in.
In your case there are two inputs D and SI. That's why I'm confused.

a classic code is

process(clk,reset)
begin
if rising_edge(clk)
if (reset='1') then
data<="0000";
else
data<=SI&data(3 downto 1);
end if;
end if;
end process;


then currently I don't understand how you can use SI and D input simultaneously