mangohaha
Newbie level 5
Thanks!
I just start to learn the VHDL, based on my understanding, as a kind of digital IC design language, it only can be used on FPGA or PLD
If so, although I know we can use the netlist, puting into cadence to get the layout. But why? why not just use the fpga or pld?
I just start to learn the VHDL, based on my understanding, as a kind of digital IC design language, it only can be used on FPGA or PLD
If so, although I know we can use the netlist, puting into cadence to get the layout. But why? why not just use the fpga or pld?