why do we need lay out based on VHDL

[mangohaha]

Thanks!
I just start to learn the VHDL, based on my understanding, as a kind of digital IC design language, it only can be used on FPGA or PLD
If so, although I know we can use the netlist, puting into cadence to get the layout. But why? why not just use the fpga or pld?

 

[TrickyDicky]

you can also use VHDL to design an ASIC.

But I dont really understand your question. FPGAs are just elements on a PCB, and VHDL is not suitable for PCB design.

 

[shaiko]

I think you're mixing FPGA/ASIC netlists and PCB schematic netlists.
Even though the term "netlist" is used in both fields it describes 2 different things:

1. FPGA/ASIC netlist - describes connection between logic components inside a digital integrated circuit.
2. PCB netlist - describes connections between components on your printed circuit board

 

[mangohaha]

you can also use VHDL to design an ASIC.

But I dont really understand your question. FPGAs are just elements on a PCB, and VHDL is not suitable for PCB design.

Thanks tricky!
for example, because I want to design a chip, like a memory with VHDL. I can use the fpga, also the other way, I can layout(asic) (use cadence based on the netlist from xilinx) by myself, right? Which way is better?

 

[joelby]

Depends if you want to target an FPGA or an ASIC. It's a lot faster and cheaper to prototype with an FPGA.

If you are using Xilinx-specific primitives and hard IP (e.g. clock management blocks, BRAM, transceivers, etc.), bear in mind they won't exist in ASIC libraries so it might not be as simple as just re-using the netlist.

 

[AMCC]

Hi,
Suppose you are a designer responsible for designing a schematic of some PCB. Suppose your schematic contains an FPGA... with something like 1200 pins...
Now suppose that the guy that develops the VHDL for the FPGA... doesn't give you the full pin assignment until "five minutes" before you send the PCB for manufacturing...
Would you like to hand-assign the pinout from the FPGA designer in your Schematic? (Don't answer )..
So... most advanced tools (like Mentor... or a believe Cadence) provide a way to do THAT automatically.
You shouldn't have to "draw" an FPGA component... all the pinout will come directly from the FPGA firmware design tools.

 

[TrickyDicky]

you still have to assign your pins from the top level of your VHDL to the FPGA pins by hand.

 

[AMCC]

you still have to assign your pins from the top level of your VHDL to the FPGA pins by hand.

If you have access to tools like IODesigner (from Mentor Graphics) this is fully automatic, unless you specifically want to assign a given pin to a given signal. The "communication" between Synthesis tool and Schematic/PCB tool is automatic and requires no user intervention.