matrixofdynamism
Advanced Member level 2
While a testbench can be written that treats the DUT as a black box i.e provide input stimulus and then compare the output with expected values, it would be advantageous to be able to assert values of internal signals also in RTL simulation. I understand that this may not be possible once the design has been synthesized which will change the internal details of the design.
All the examples and application notes I have seen of VHDL testbench yet create a testbench which only looks at the top level signals of the entity under test. Is looking inside the DUT to create a testbench that is more thorough in its verification activity discouraged? I have heard/read that VHDL 2008 includes the possibility to use hierarchical signal names. However, all tools may not support it yet.
So my question is, why don't I find testbench examples that use hierarchical signals in the DUT to verify the design? Is it not "orthodox" practice yet or does it have some serious drawbacks?
All the examples and application notes I have seen of VHDL testbench yet create a testbench which only looks at the top level signals of the entity under test. Is looking inside the DUT to create a testbench that is more thorough in its verification activity discouraged? I have heard/read that VHDL 2008 includes the possibility to use hierarchical signal names. However, all tools may not support it yet.
So my question is, why don't I find testbench examples that use hierarchical signals in the DUT to verify the design? Is it not "orthodox" practice yet or does it have some serious drawbacks?