why design compiler change my FF output naming?

[ronnie710409]

ff output

dear all:
why synopsis DC using wire naming replace my Reg. naming after synthsis? For example, i declare " reg [7:0] A; " in my rtl code, and the instance name of A[0] is A_reg_0_, but the Q output of the FF is "n2214" instead of A naming. Could u tell me why? thanks a lot.

 

[rsrinivas]

design compiler naming rule

Yes synopsys does this.
If u see from the code(Verilog netlist) the output of ur FF(Q) will somewhere connected to ur output and say ur output signal names is "opt". name "opt" will not be changed. as ur Q output ,if it is connected to say opt then the wire n2214 will be assigned to ur opt.
Dc only keeps ur specified input output names as specified by you. all other signals are considered as internal (say wires) to the design and it assigns a name for it.
However u can change the naming style.
the naming should not cause any problems to u...
refer to the dc manual for more info.

Regards
Srinivas

 

[ronnie710409]

dear Srinivas and all:
if the Reg output doesn't connect to output port, how should i restrict DC not to rename it. Does any constraint can do this? i've report the naming rule, but still dont know how to fix it. it's actually bad to trace when running post-sim. thanks a lot.

 

[raul_777_h]

Hi ronnie710409:
you can try to use dont touch option, which can remain the name you want.