jayfcam
Newbie level 6
Hi,
I ham having a design where bus have to travel 4mm of distance in 28nm design. What i am seeing is that clock signal gets inverted after every re timer stages but data bits does not. How does this kind of configuration help?
Regards,
Jay
I ham having a design where bus have to travel 4mm of distance in 28nm design. What i am seeing is that clock signal gets inverted after every re timer stages but data bits does not. How does this kind of configuration help?
Regards,
Jay