hamidkavianathar
Member level 5
why can't I write into the memory?
hi guys
I want to write something into a memory. I using Kintex7 FPGA and vivado. I'm writing into memory according to this figure.
but the app_wdf_rdy is always low. could you tell me, what should I do?
here is my source code:
- - - Updated - - -
when I assert the app_wdf_end, the app_wdf_rdy gets stuck low, and when I deassert the app_wdf_end signal, it goes high. I just want to write a 32 bits and read it, so I think that I must assert the app_wdf_end signal. I read something in this page:
http://www.xilinx.com/support/answers/37023.html
but it is virtex 6.
thanks.
hi guys
I want to write something into a memory. I using Kintex7 FPGA and vivado. I'm writing into memory according to this figure.
but the app_wdf_rdy is always low. could you tell me, what should I do?
here is my source code:
Code:
`timescale 1ns / 1ps
//`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09/25/2016 09:56:26 AM
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module top(
input wire clk_50,
output led1,
output led2,
output led3,
output led4,
output led5,
// Memory interface ports
output [15:0] ddr3_addr, // output [15:0] ddr3_addr
output [2:0] ddr3_ba, // output [2:0] ddr3_ba
output ddr3_cas_n, // output ddr3_cas_n
output [0:0] ddr3_ck_n, // output [0:0] ddr3_ck_n
output [0:0] ddr3_ck_p, // output [0:0] ddr3_ck_p
output [0:0] ddr3_cke, // output [0:0] ddr3_cke
output ddr3_ras_n, // output ddr3_ras_n
output ddr3_reset_n, // output ddr3_reset_n
output ddr3_we_n, // output ddr3_we_n
inout [31:0] ddr3_dq, // inout [63:0] ddr3_dq
inout [3:0] ddr3_dqs_n, // inout [7:0] ddr3_dqs_n
inout [3:0] ddr3_dqs_p, // inout [7:0] ddr3_dqs_p
//output init_calib_complete, // output init_calib_complete
output [0:0] ddr3_cs_n, // output [0:0] ddr3_cs_n
output [3:0] ddr3_dm, // output [7:0] ddr3_dm
output [0:0] ddr3_odt // output [0:0] ddr3_odt
);
parameter state_0 = 0;
parameter state_read = 1;
parameter state_write = 2;
//parameter state_read_r = 3;
//parameter state_write_r = 4;
//parameter state_compare = 5;
reg [1:0] current_state = state_0;
reg [1:0] next_state;
wire clk_100;
wire clk_200;
reg [29:0] app_addr;
reg [2:0] app_cmd;
reg app_en;
reg [511:0] app_wdf_data;
reg app_wdf_end;
reg app_wdf_wren;
wire [255:0] app_rd_data;
wire app_rd_data_end;
wire app_rd_data_valid;
wire app_rdy;
reg app_zq_req;
reg app_sr_req;
reg app_ref_req;
wire app_sr_active;
wire app_ref_ack;
wire app_zq_ack;
reg [63:0] app_wdf_mask;
reg reset;
wire [31:0] count;
wire init_calib;
reg enable;
reg app_wdf_end;
clk_wiz_0 instance_name
(
// Clock in ports
.clk_in1(clk_50), // input clk_in1
// Clock out ports
.clk_out1(clk_100), // output clk_out1
.clk_out2(clk_200), // output clk_out2
// Status and control signals
.reset(1'b0), // input reset
.locked()); // output locked
counter counting(
.clk(clk_100),
.reset(reset),
.count(count),
.en(enable)
);
mig_7series_0 u_mig_7series_0 (
// Memory interface ports
.ddr3_addr (ddr3_addr), // output [15:0] ddr3_addr
.ddr3_ba (ddr3_ba), // output [2:0] ddr3_ba
.ddr3_cas_n (ddr3_cas_n), // output ddr3_cas_n
.ddr3_ck_n (ddr3_ck_n), // output [0:0] ddr3_ck_n
.ddr3_ck_p (ddr3_ck_p), // output [0:0] ddr3_ck_p
.ddr3_cke (ddr3_cke), // output [0:0] ddr3_cke
.ddr3_ras_n (ddr3_ras_n), // output ddr3_ras_n
.ddr3_reset_n (ddr3_reset_n), // output ddr3_reset_n
.ddr3_we_n (ddr3_we_n), // output ddr3_we_n
.ddr3_dq (ddr3_dq), // inout [63:0] ddr3_dq
.ddr3_dqs_n (ddr3_dqs_n), // inout [7:0] ddr3_dqs_n
.ddr3_dqs_p (ddr3_dqs_p), // inout [7:0] ddr3_dqs_p
.init_calib_complete (init_calib_complete), // output init_calib_complete
.ddr3_cs_n (ddr3_cs_n), // output [0:0] ddr3_cs_n
.ddr3_dm (ddr3_dm), // output [7:0] ddr3_dm
.ddr3_odt (ddr3_odt), // output [0:0] ddr3_odt
// Application interface ports
.app_addr (count[29:0]), // input [29:0] app_addr
.app_cmd (app_cmd), // input [2:0] app_cmd
.app_en (app_en), // input app_en
.app_wdf_data (32'hAAAA0000), // input [511:0] app_wdf_data
.app_wdf_end (app_wdf_end), // input app_wdf_end
.app_wdf_wren (app_wdf_wren), // input app_wdf_wren
.app_rd_data (app_rd_data), // output [511:0] app_rd_data
.app_rd_data_end (app_rd_data_end), // output app_rd_data_end
.app_rd_data_valid (app_rd_data_valid), // output app_rd_data_valid
.app_rdy (app_rdy), // output app_rdy
.app_wdf_rdy (app_wdf_rdy), // output app_wdf_rdy
.app_sr_req (1'b0), // input app_sr_req
.app_ref_req (app_ref_req), // input app_ref_req
.app_zq_req (app_zq_req), // input app_zq_req
.app_sr_active (), // output app_sr_active
.app_ref_ack (app_ref_ack), // output app_ref_ack
.app_zq_ack (app_zq_ack), // output app_zq_ack
.ui_clk (ui_clk), // output ui_clk
.ui_clk_sync_rst (), // output ui_clk_sync_rst
.app_wdf_mask (app_wdf_mask), // input [63:0] app_wdf_mask
// System Clock Ports
.sys_clk_i (clk_100),
// Reference Clock Ports
.clk_ref_i (clk_200),
.sys_rst (1'b1) // input sys_rst
);
assign led1 = app_rd_data_valid;
assign led2 = app_rdy;
assign led3 = app_wdf_rdy;
assign led4 = |app_rd_data;
assign led5 = app_rd_data_end;
always @ (posedge ui_clk)
begin
current_state <= next_state;
end
always @( current_state )
begin
case( current_state )
state_0: begin
enable <= 1'b0;
app_en <= 1'b0;
reset <= 1'b1;
app_wdf_end <= 1'b0;
app_cmd <= 3'b000;
app_wdf_wren <= 1'b0;
app_zq_req <= 1'b0;
app_ref_req <= 1'b0;
app_wdf_mask <= 64'h0000000F;
if ( init_calib_complete == 1'b1)
next_state <= state_write;
else
next_state <= state_0;
end
state_write: begin
//enable <= 1'b0;
app_en <= 1'b1;
//reset <= 1'b0;
app_cmd <= 3'b001;
app_wdf_wren <= 1'b1;
app_zq_req <= 1'b0;
app_ref_req <= 1'b0;
app_wdf_mask <= 64'h0000000F;
app_wdf_end <= 1'b0;
if( app_wdf_rdy == 1'b1 )
begin
enable <= 1'b1;
if( count >= 32'h0000F00 )
begin
next_state <= state_read;
reset <= 1'b1;
end
else
begin
next_state <= state_write;
reset <= 1'b0;
end
end
else
begin
enable <= 1'b0;
next_state <= state_write;
reset <= 1'b0;
end
end
state_read: begin
//enable <= 1'b0;
app_en <= 1'b1;
app_wdf_end <= 1'b0;
//reset <= 1'b0;
app_cmd <= 3'b000;
app_wdf_wren <= 1'b0;
app_zq_req <= 1'b0;
app_ref_req <= 1'b0;
app_wdf_mask <= 64'h0000000F;
app_wdf_end <= 1'b0;
if( app_rdy == 1'b1 )
begin
enable <= 1'b1;
if( count >= 32'h0000F00 )
begin
next_state <= state_0;
reset <= 1'b1;
end
else
begin
next_state <= state_read;
reset <= 1'b0;
end
end
else
begin
enable <= 1'b0;
next_state <= state_read;
reset <= 1'b0;
end
end
endcase
end
endmodule
- - - Updated - - -
when I assert the app_wdf_end, the app_wdf_rdy gets stuck low, and when I deassert the app_wdf_end signal, it goes high. I just want to write a 32 bits and read it, so I think that I must assert the app_wdf_end signal. I read something in this page:
http://www.xilinx.com/support/answers/37023.html
but it is virtex 6.
thanks.
Last edited: