garvind25
Full Member level 3
Hi,
As I know clock can be detected in VHDL through the following constructs:
My query is if this is true. Also, I was wondering if the second way (rising_edge) will detect an edge if there is a transition from ‘X’ to ‘1’.
Thanks,
Arvind Gupta.
As I know clock can be detected in VHDL through the following constructs:
- clock’event and clock =’1’
- rising_edge(clock)
My query is if this is true. Also, I was wondering if the second way (rising_edge) will detect an edge if there is a transition from ‘X’ to ‘1’.
Thanks,
Arvind Gupta.