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I mean that considering on BackEnd Engineering. If statement and assignment combinational logic, which one has more advantage. For example, comparing between them on the aspect of number of gate counts it may occupy and the delay it may have.
Thank you
W3Y
actually there is no difference between statement and assignment when implementing comb logic .
The only demerit of statement is that: the old 1995-syntax of verilog is easy to infer unwanted latch. But new 2001-syntax eliminate this shortage.
As to a designer's aspect, also implementation aspect, no difference.
Even to simulaton, no speed difference also.
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