where to back_annotate SDF

[xworld2008]

sdf_annotate worst case

After synthesizing ,the DC generates the .sdf file and .v netlist file . Then , I want to do the GATE level simulation .I don't know to back_annotate the SDF file to source code or .v(netlist file generated by DC). it's as follow:
1> source code file + .sdf file
or
2> .v(netlist file by DC) + .sdf file


and THE FPGA is the same to the ASIC

THANKS!

 

[eternal_nan]

what is worst case and best case sdf

The sdf annotiation is done by invoking the verilog system task:
$sdf_annotate() in your testbench verilog code. You will need to supply
the command with a filename as well as some options (best case/typ
case/ worst case number choice and such).

 

[sandusty]

you need to use your gate level netlist to run back annotate simulation.

Check your sdf... you will know it can NOT work with your rtl source code.

 

[balik]

After synthesis you need some files to simulate netlist.
1. You need your netlist of course
2. You need sdf file
3. You need all verilog libraries which you use on design. Usually it is cell library, memory blocks.

In testbench you need to run command $sdf_annotate(). If you will not annotate your delays you still of course can simulate design but in this case simulator will use some default delays from cell library.