post sim without sdf

[qqxiu]

Hi all,
I'm new in VLSI.
Recently, I run the postsim without sdf, that cause some of my test pattern failed. When I simulate with sdf, everything will be fine. I wondering why this will happened. Could anyone point out some knowledge that I miss? Thanks a lot.

 

[rca]

do you clarify the differences between a RTL and a postsim netlist? That should help.

 

[ThisIsNotSam]

by postsim netlist, I am assuming you mean a gate level netlist of a digital design. it is very common that a netlist will fail to simulate properly if it has no annotated delays. you can easily fall into traps set by the simulation models, like flip flops with impossible hold times. I have seen so many good designers spend hours trying to understand these simulations and come up empty handed because the assumptions are wrong.

 

[rca]

by postsim netlist, I am assuming you mean a gate level netlist of a digital design. it is very common that a netlist will fail to simulate properly if it has no annotated delays. you can easily fall into traps set by the simulation models, like flip flops with impossible hold times. I have seen so many good designers spend hours trying to understand these simulations and come up empty handed because the assumptions are wrong.

my question was to trig an analyze by qqxiu to understand the diff...