When power up, what value is in CPLD's register?

[wwwrabbit]

I don't have dedicated reset signal in my project. I wonder when power up what's the value of my register inside CPLD? Does CPLD clean all the registers when power up?
Do I need to define a reset signal for the Chip? :?:

 

[cube007]

Hello wwwrabbit,

a CPLD has no reset logic inside. You should build up an external power on reset logic and wire it to a dedicated input to reset (by coding) the needed registers in the CPLD.

e.g.

if mrst = '0' then
tmr0 <= TMR0_RESET;
-- activities triggered by rising edge of clock
elsif clk'event and clk = '1' then
tmr0 <= tmr0_nxt;
end if;


Bye,
cube007

 

[Hero]

Hi,

You need external reset chip to provide stable power-up values.

After reset all FFs are cleared.

Power-up value of register variable depends on varaible definition.

If you define register variable as FF with non-inverted output, power-up value is 0. If you define register variable as FF with inverted output, power-up value is 1.

These definitions are very important for defining state-machine power-up state and logic optimization.

These considertions depend on CPLD architecture. If some FFs in CPLD don't have output inverting capability, you cannot change power-up value.

Regards

 

[wwwrabbit]

Thank you for your reply. but I still have questions.
I use Altra EPM128S. how can I define a register variable as a FF with non-inverted output? in verilog language we define a variable like this,
reg abc;
there is no way to tell it is FF with non-inverted output or it is FF with inverted output.

:?:

 

[wwwrabbit]

Thank you for your reply. but I still have questions.
I use Altra EPM128S. how can I define a register variable as a FF with non-inverted output? in verilog language we define a variable like this,
reg abc;
there is no way to tell it is FF with non-inverted output or it is FF with inverted output.

:?:

 

[cube007]

Hello wwwrabbit,

Normally you don’t define a dedicated FF for example a DFF. In VHDL you define a signal which will be a register to store the information. VHDL and Verilog are languages for programming in register transfer level (RTL) and not in gate level.
Which language do you want to use? Could you explain your problem in detail please?

Bye,
cube007

 

[Smanetto]

Probably you mean EPM7128S.

Altera CPLDs (and also FPGAs) always start with FF at zero, if you don't use asyncronous preset with a dedicated "reset" net.

It is true that if you have an inverter after the FF you have "1", but the FF is still "zero".

Remember, to avoid problems with spikes or disturbs on the power supply (believe me, before or after it will happen!), it is always a good idea use a reset or a similar way to put your state machines at a known state.

To have the complete control of Altera devices use AHDL language. It is very simple and powerful.

Bye

 

[wwwrabbit]

Hi everybody,
I figured it out as per your inspiration.
I use verilog language. when power up the register's value is zero.
This was proved in the target board.
Thanks for you guys help.

wwwrabbit.

 

[Hero]

Hi,

In the ABEL-HDL you can use these constructions for power-up and polarity definition.

reg1 node istype 'reg_D, invert'; // power-up HI
reg2 node istype 'reg_D, buffer'; // power-up LO

It is so simple.

Regards