What should I do----no negedge clock_gating_cell ?

[wjccentury]

Hello, all guys,
In my library, I only have posedge clock_gating_cell, so for negedge flip-flop, I can't insert clock gating cell as my wish.
After synthesis, I found because of no negedge clock_gating_cell, PowerCompiler creates them by latch and logic gates, but when I do scan insertion, scan clock can't go through these kind of negedge clock_gating_cell.
What should I do?
Hope for your reply !!! Thanks !

 

[sesl33]

Maybe you can try to change your code before the power compiler. i.e. you invert the clock before you pass the clock to the posedge clock_gating cell. This way, it will be negedge triggered.

Then, you add multiplexors so that during scan, you bypass the original clock and use your scan clock.

 

[wjccentury]

Maybe you can try to change your code before the power compiler. i.e. you invert the clock before you pass the clock to the posedge clock_gating cell. This way, it will be negedge triggered.

Then, you add multiplexors so that during scan, you bypass the original clock and use your scan clock.

Yes, you're right. At present I used I multiplexors to solve this problem.

But as you said, if I insert posedge clock_gating cell after an inverter, during scan test, all test clock should be in off-state, but after an inverter, this clock is in active-state. And this state can not initialize the following posedge clock_gating cell. This will cause X value from clock_gating_cell.