wjccentury
Junior Member level 2
Hello, all guys,
In my library, I only have posedge clock_gating_cell, so for negedge flip-flop, I can't insert clock gating cell as my wish.
After synthesis, I found because of no negedge clock_gating_cell, PowerCompiler creates them by latch and logic gates, but when I do scan insertion, scan clock can't go through these kind of negedge clock_gating_cell.
What should I do?
Hope for your reply !!! Thanks !
In my library, I only have posedge clock_gating_cell, so for negedge flip-flop, I can't insert clock gating cell as my wish.
After synthesis, I found because of no negedge clock_gating_cell, PowerCompiler creates them by latch and logic gates, but when I do scan insertion, scan clock can't go through these kind of negedge clock_gating_cell.
What should I do?
Hope for your reply !!! Thanks !