fouwad
Full Member level 4
What is wrong with this Mux code using indexing
and here is its test bench, The code is synthesizing but when i run the simulation, the index is showing the negative value and simulation wont start
Code:
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-- Company:
-- Engineer:
--
-- Create Date: 14:48:40 09/27/2018
-- Design Name:
-- Module Name: Mux256 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Mux256 is
Port ( inp : in STD_LOGIC_VECTOR (255 downto 0);
sel : in STD_LOGIC_VECTOR (7 downto 0);
outp : out STD_LOGIC);
end Mux256;
architecture Behavioral of Mux256 is
signal sig_sel: integer;
signal sig_sel1: unsigned (7 downto 0);
begin
sig_sel1 <= unsigned(sel);
sig_sel <= CONV_INTEGER(sig_sel1);
process(inp, sel)
begin
outp <= inp(sig_sel);
end process;
end Behavioral;
and here is its test bench, The code is synthesizing but when i run the simulation, the index is showing the negative value and simulation wont start
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Demux256 is
Port ( inp : in STD_LOGIC;
sel : in STD_LOGIC_VECTOR (7 downto 0);
outp : out STD_LOGIC_VECTOR (255 downto 0));
end Demux256;
architecture Behavioral of Demux256 is
signal temp_out: std_logic_vector (255 downto 0);
signal sig_sel: integer;
signal sig_sel1: unsigned (7 downto 0);
begin
sig_sel1 <= unsigned(sel);
sig_sel <= CONV_INTEGER(sig_sel1);
process(inp, sel)
begin
if(inp = '1') then
temp_out(sig_sel) <= '1';
else
temp_out <= (others => '0');
end if;
end process;
outp <= temp_out;
end Behavioral;