Bhuvana Eshwari
Newbie level 3
what is the major difference between verilog HDL and VHDL????
Which is best in designing the AMBA AHB, ASB,APB,AXI?????
Which is best in designing the AMBA AHB, ASB,APB,AXI?????
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The biggest difference is VHDL's a strongly typed language and is significantly more verbose than Verilog.what is the major difference between verilog HDL and VHDL????
Which is best in designing the AMBA AHB, ASB,APB,AXI?????