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hi,
i think the layer stack depends on your design. in the figure posted below there are example layer stacks up to 8 layers (source: Signal Integrity Issues and Printed Circuit Board Design). But they can differ, depending on your requirements (e.g. the count of signal layer / power layer, do you have different power source (digital/analog) ...)
greetings,
hqqh
For EMI reduction, the ground and power planes should be symmetrical with respect to the center of the board. The high speed signals should be on internal layers next to the ground plane. Low speed signals can be further away.
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gnd
sig1
gnd
sig2---care must be taken that routes dont come in the split in this layer
pwr1
pwr2
sig3---care must be taken that routes dont come in the split in this layer
gnd
sig4
gnd
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