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what is the effective resistance of series NMOS ?

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sevid

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hi, everyone

"For pull down time of a 4-input NAND gate, due to velocity saturation, the effective resistance of the four series NMOS will be reduced, so you will not see a 4Rn but less may be 2.5Rn to 3Rn. "

can u explain it clearly ?

plz
and
thanks

sevid
 

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