what is the backend design flow

[tybhsl]

synopsys low power steps back end

what is the backend design flow and what is the corresponding eda tools needed? Thanks a lot!

 

[wadaye]

front end & backend asic design flow

Hi,

There are many backend flow accroding the tool you use. The P&R of Cadence is

SE/Soc Encounter, of synopsys is appllo/Astro and magma also have backend

tools. For detail backend flow you can find the in Fab's(TSMC, UMC etc) website.

 

[AlexWan]

basics of backend design floorplanning

From the point of view RTL designer, flow is:

Synthesis-->Pre-simulation/STA/Formal-->P&R/CTS-->Post-simulation/STA/Formal-->Type-out

 

[videohu]

backend flow

The above include front end design and back end design, the separating point is STA/Formal. Now the speperating front end and back end is not clear. The designer of front end need the support of back end guy.

 

[gabi71ro]

backend designer

For custom design (full custom layout mask) the work flow is:

Schematic (Cohesion - Silicon Canvas Laker - Cadence schematic editor ) / simulations ( HSPICE - Spectre) / Full custom layout (one of Virtuoso - Laker - LEDIT - Taner...LASI) / DRC & LVS & PEX (one of Calibre - Magma - Dracula - Assura - Diva...) / Post layout simulation ( for small designs with less than 50K transistors HSPICE - Spectre; for chip level HSIM) / tape-out.

Note:
If the design is digital, then after simulations is beter to translate the spice netlist (or others) in verilog/vhdl in order to check that the schematics will do what you want to be!

Best Regards.

 

[floatgrass]

backend designer flow

1 floorplan
2prouting net
3 placement
4 cts
5 routing
6 drc/lvs
7 gdstii out

 

[hahaguy2]

what does backend design mean?

For synopsys tools:
1. Synthesis (Design Compiler)
2. Floorplan (Jupiter)
3. Placement (Physical Compiler)
4. Routing (Astro)
5. Verification (Hercules, Formality, Primetime)

 

[gold_kiss]

back end flow sta and layout

The actual process where in you map your HDL code (RTL) to physical gates/transistors is backend process.
You involve following steps here
a) Synthesis
b)floor planning
c) Placement
d) routing
e) clock insertion (clock tree synthesis)
f) timing check
g)tapeout

Cheers,
Gold_kiss

 

[zhangpengyu]

backend design flow

floor plan
P&R
CTS
STA
tapeout

 

[mst]

backend design digital floorplan

every tool has different flow ..what tool you are using

 

[tybhsl]

design flow backend

Thanks everyone!
In your replies, what do you refer "cts" as? I mean, what's the full name of cts? Thanks!

Added after 2 minutes:

Thanks!
Could you please list me some web sites of Fab's(TSMC, UMC etc) website? Thanks!

 

[wilfwolf]

goal of a digital backend design flow

For Mentor tools:
1.Physical layout design(IC station,CDS SE,Apolo)
2.parasitic abstracting and delay calculation(Xcalibre)
3.Physical verification and post simulation(calibre)

 

[omid219]

soc backend design flow

CTS means "clock tree synthesis"

 

[arunragavan]

Synopsys's ASTRO tools is Clock tree synthesis. Low power design can be achieved by this CTS tool..

take a look at this

h**p://www.synopsys.com/news/pubs/compiler/art2_power-dec04.html

wud help u understand and more abt cts

with regards,

 

[smith_kang]

hi
the backend design flow is as follows
1.Floorplanning
2.Synthesis
3.Final Placement
4.Clock Design
5.Scan Chain Optimization
6.Routing
7.Physical Verification

for backend you can use Cadence BuildGates,
Synopsys design compiler

 

[abhineet22]

whenever u complete the first part thatis front end that is
designentry vhdl->simulation(functional)->synthesis--------front end
after that backend comes that is
simulation(timing)->edif file generation->floorplanning->routing->placement->downloading in to kit
the tool used for backends are
synopsys,avanti,magma,mentor graphics,cadence.

 

[jitendra]

Hi,
Can any body give link for some document about backend flow ?

Thanks,
Jitendra

 

[amarnath]

search the forum.u will find some.

regards
amarnath