pankaj
Member level 3
Regarding Synthesis
Hello,
What happens generally when we specifying addition of two nos in any hdl,
eg. a : In Std_logic_vector(31 Downto 0);
b : In Std_logic_vector(31 downto 0);
sum : Out Std_Logic_vector(31 Downto 0)
sum <= a + b;
Will the synthesizer synthesize the adder using ripple carry or carry-lookahead. Specifically what does Xilinx ISE7.1i will do
Pankaj
Hello,
What happens generally when we specifying addition of two nos in any hdl,
eg. a : In Std_logic_vector(31 Downto 0);
b : In Std_logic_vector(31 downto 0);
sum : Out Std_Logic_vector(31 Downto 0)
sum <= a + b;
Will the synthesizer synthesize the adder using ripple carry or carry-lookahead. Specifically what does Xilinx ISE7.1i will do
Pankaj