what happens if i give a weak 0 to a not gate;what would be the strength of output be

[kaushikrvs]

and what would be the case if a supply 1 and a weak 1 are inputs to an and gate ? what would be the output strength and logic?

 

[dave_59]

I'm assuming you are talking about a Verilog description. Strengths of the inputs do not affect the strength of the output of logic primitives gates. Only the MOS and tran primitives pass strength.

 

[ThisIsNotSam]

and what would be the case if a supply 1 and a weak 1 are inputs to an and gate ? what would be the output strength and logic?

check dave's answer. signal strength is never used when writing verilog in RTL form.