gahelton
Newbie level 4
First, I'm sorry if this is a re-hash of any existing posts, many of which I have read. But I think that a watchdog timer would be useful for my design.
This one seems relevant.
https://www.edaboard.com/threads/watchdog-reset-for-fpga-designs.247625/
The way that a watchdog would have to work is different than with a microcontroller design. For microcontrollers, the logic is sequential while on the FPGA it is highly parallel.
The way that I would envision a watchdog to work for a FPGA would be to have each critical, clocked process write to a large watchdog register when it has completed. All the bits of register would be logically "ANDed" together, and the output from the AND would reset the watchdog timer. If any process failed or locked up, the watchdog timer would not be satisfied, and force an internal reset. Anytime the watchdog timer is reset (all processes have set their respective bits saying that "I'm ok", then the watchdog register would be cleared in addition to the timer). The watchdog timer would need to be setup to timeout for the longest possible process in the system. Some processes will run in a clock cycle or two, and some may not be satisfied with it's logic for dozens of clock cycles.
One person suggested that each process with a state machine could provide it's own state reset in the event of a hang-up. While that would be nice, I think that would require a lot more resources since I have a lot of processes.
What is the best practice for providing a watchdog for a FPGA design ?
Thanks.
This one seems relevant.
https://www.edaboard.com/threads/watchdog-reset-for-fpga-designs.247625/
The way that a watchdog would have to work is different than with a microcontroller design. For microcontrollers, the logic is sequential while on the FPGA it is highly parallel.
The way that I would envision a watchdog to work for a FPGA would be to have each critical, clocked process write to a large watchdog register when it has completed. All the bits of register would be logically "ANDed" together, and the output from the AND would reset the watchdog timer. If any process failed or locked up, the watchdog timer would not be satisfied, and force an internal reset. Anytime the watchdog timer is reset (all processes have set their respective bits saying that "I'm ok", then the watchdog register would be cleared in addition to the timer). The watchdog timer would need to be setup to timeout for the longest possible process in the system. Some processes will run in a clock cycle or two, and some may not be satisfied with it's logic for dozens of clock cycles.
One person suggested that each process with a state machine could provide it's own state reset in the event of a hang-up. While that would be nice, I think that would require a lot more resources since I have a lot of processes.
What is the best practice for providing a watchdog for a FPGA design ?
Thanks.