Want a discussion on Folded mesh biasing scheme-minimum selector class ab output

[ivyahoney]

Hello, all,

I want to design an amplifier that can driving large capacitor load, in order of ~mF before the circuit is stable.

I want to use this minimum selector output control circuit (shown in the attachement) to achieve the high dynamic output current, and in the same time keep the quiescent current as low as possible.

In my design, the transistor ratio (W/L) is very small.

Problem is, when the output stage is driving large current source (or sink) from VDD (or to GND), the two output transistor are going to linear region. I want to have a output current ability about several hundreds microampere.

What kind of considerations should I take?

Anyone who has any suggestions, please be kind to tell me, thanks a lot!

Ref.
Kclass-Jan de Langen, J.H. Huijing, “Compact low-voltage Power-Efficient Operational Amplifier Cells for VLSI,” in IEEE Journal of solid-state circuits

 

[erikl]

How much is your I_BIAS now? You might either increase it, or increase both M100/M110 and M101/M111 ratios (which currently = 20).
These (equal) ratios should be about (max. output current) / I_BIAS .

 

[ivyahoney]

How much is your I_BIAS now? You might either increase it, or increase both M100/M110 and M101/M111 ratios (which currently = 20).
These (equal) ratios should be about (max. output current) / I_BIAS .

First, erikl, thanks for your quick reply.
Yes, the problem is to keep the static power consumption low in the meaning time to enlarge the dynamic output current.
I got to know that TI has a gas sensor interface chip LMP91000. The opamp it utilized has the same minimum selector structure, and the static power consumption is only about 2uA, under the supply voltage from2.7V~5.5V. The output driving capability is about +/- 750uA.
If I want to use this 2uA for the overall current consumption, I will give the current bias IBIAS dozens of nA, I think.

There are some equations to calculate the quiescent current and the maximal current in "Compact low-voltage Power-Efficient Operational Amplifier Cells for VLSI".
Do you have any more suggestions on how to design the transistor parameters to keep the static power as low as possible? Thanks!

 

[erikl]

Do you have any more suggestions on how to design the transistor parameters to keep the static power as low as possible?

As I told you above: keep I_BIAS low and rise the M100/M110 and M101/M111 ratios.

Thanks a lot for the paper. -like biasing schemes class AB amplifiers.

 

[Junus2012]

Hello

this op-amp need a compensation capacitor, as you have very high load capacitor it mean you will also have a large compensation capacitor. When you drive a capacitive load then the slew rate should be your concern and hence the minimum bias current should be able to slew the compensation at least with the minimum and in addition to the bandwidth ( it will be not interest if you are working with D.C signals slew requirement.

 

[ivyahoney]

Hello

this op-amp need a compensation capacitor, as you have very high load capacitor it mean you will also have a large compensation capacitor. When you drive a capacitive load then the slew rate should be your concern and hence the minimum bias current should be able to slew the compensation at least with the minimum and in addition to the bandwidth ( it will be not interest if you are working with D.C signals slew requirement.

It does have a large compensation capacitor, but I don't know why, here is what I think,

The load capacitor is very large (~mF) to introduce the dominant pole. If I use compensation capacitor large enough, will it be possible to degrade the phase margin? Because, the larger the miller compensation capacitor is, the nearer the second pole is from the dominant pole, I think. I don't know whether it is right to understand like this.

The input signal I am dealing with is in the range of several Hzs. So, I don't know how to consider the slew rate... Would you please be kind to help me with these problems more specifically? These problems confused me a lot, and I am still very fresh in designing circuit. Thanks for help!

- - - Updated - - -

As I told you above: keep I_BIAS low and rise the M100/M110 and M101/M111 ratios.

Thanks a lot for the paper. -like biasing schemes class AB amplifiers.

- - - Updated - - -

As I told you above: keep I_BIAS low and rise the M100/M110 and M101/M111 ratios.

You mean to low down IBIAS and rise the ratios, for example,if I give the IBIAS 10nA, and the ratio 100, and in this way, M111 perhaps gets 10nA, and M101 gets 1uA. Am I right to understand your idea?

By low down the bias current, the transistor's aspect ratio will be very, very small... Will it be correct to series several transitor (W/L) to form W/m * L, here m is the transistor number?

 

[Junus2012]

hello again

the frequency of the input signal to your amplifier has to be in the range of the amplifier GBW ( gain bandwidth product). in your case the input signal has very few frequency so the bandwidth of your op-amp will not be a problem at all.
the slew rate is defined from the load side of the amplifier, it define you how fast you need to charge and discharge the capacitor, and also dont need high slew rate as your input signal frequency is also small from this relationship

fmax <= S.R / 2.pi. Vofull...... ( for a sin signal)

 

[erikl]

You mean to low down IBIAS and rise the ratios, for example,if I give the IBIAS 10nA, and the ratio 100, and in this way, M111 perhaps gets 10nA, and M101 gets 1uA. Am I right to understand your idea?

Right. If 1µA isn't enough, you can even increase this ratio.

By low down the bias current, the transistor's aspect ratio will be very, very small... Will it be correct to series several transitor (W/L) to form W/m * L, here m is the transistor number?

I wouldn't recommend a series connection - at least not for low supply voltage circuits. Better increase L.

But you could keep the original W/L ratios - this is no pb. with the used current control methodology - the transistors just work in weak(er) inversion mode. Would be a pb. if you need high GBW - but not in the several Hzs range ;-)

If you keep the original W/L ratios, the only pb. is - with very high M100/M110 and M101/M111 ratios - that you'll get huge output transistors.

 

[ivyahoney]

Right. If 1µA isn't enough, you can even increase this ratio.


I wouldn't recommend a series connection - at least not for low supply voltage circuits. Better increase L.

But you could keep the original W/L ratios - this is no pb. with the used current control methodology - the transistors just work in weak(er) inversion mode. Would be a pb. if you need high GBW - but not in the several Hzs range ;-)

If you keep the original W/L ratios, the only pb. is - with very high M100/M110 and M101/M111 ratios - that you'll get huge output transistors.

I want to realize this class ab circuit in 130nm process which is different from the paper, so I have to change the transistor's aspect ratio. And, the maximum length is 10um, so I have to series the transistors, I think.

Actually, after I have simulated the circuit, I found that the maximum output current is very limited, far away from the theoretical value.

The LMP91000 have 2uA static power consumption, but can output 750uA current.

In my circuit implented in 130nm process, the output current can only get to about 100uA. The range is limited by the vds voltage of the two output resistor. Because when one transistor is output a high current, the other transistor is likely to go to linear region.

Any other suggestions or consideration on this problem? to enlarge the output current range?

Another basic problem is, what is the standard to keep the transistor work in weak inversion mode, what is the recommended vgsteff(vgs-vth) or the overdrive voltage? I am using ~100mV for the overdrive voltage now.

Thanks for your help, any question, please let me know. Thanks!

 

[erikl]

... the maximum length is 10um, so I have to series the transistors, I think.

Where would you need a transistor with L≧10µm? Should you mean width instead, you can easily finger them (parallel connection).

Actually, after I have simulated the circuit, I found that the maximum output current is very limited, far away from the theoretical value.

Probably due to series resistance.

The LMP91000 have 2uA static power consumption, but can output 750uA current.

What is LMP91000 ?

In my circuit implented in 130nm process, the output current can only get to about 100uA. The range is limited by the vds voltage of the two output resistor. Because when one transistor is output a high current, the other transistor is likely to go to linear region.

Doesn't matter: probably with rather low current (if your AB stage works correctly).

Any other suggestions or consideration on this problem? to enlarge the output current range?

Yes. Increase the current ratio. For the layout: put the ratio transistors in mid of the output transistors!

Another basic problem is, what is the standard to keep the transistor work in weak inversion mode, what is the recommended vgsteff(vgs-vth) or the overdrive voltage? I am using ~100mV for the overdrive voltage now.

With an overdrive voltage vgsteff(vgs-vth)≈100mV you're operating the transistor in moderate inversion mode; weak inversion would begin at vgsteff ≦ -50mV. The output transistors have to work in strong inversion mode anyway.

 

[ivyahoney]

Where would you need a transistor with L≧10µm? Should you mean width instead, you can easily finger them (parallel connection).


Probably due to series resistance.

What is LMP91000 ?


Doesn't matter: probably with rather low current (if your AB stage works correctly).

Yes. Increase the current ratio. For the layout: put the ratio transistors in mid of the output transistors!


With an overdrive voltage vgsteff(vgs-vth)≈100mV you're operating the transistor in moderate inversion mode; weak inversion would begin at vgsteff ≦ -50mV. The output transistors have to work in strong inversion mode anyway.

Thanks for your reply!
Q1---I am using transistors with their W<<L beacause of small current.
Q2---There are some equations to calculate the max. current and min. current of the output stage. As the author said, M110 and M111 should have the same vgsteff (vgs-vth) in order to maintain the class ab signal at the gate of M2031. Right now, I found it difficult to realize this two transistors' vgsteff equal, because, there are two different operation regions of M115 during push and pull hardly. When M100 is pushing hardly, M115 is in saturation region, M101 will have a minimum current realized by the class ab control circuit. When M101 is pull hardly, M115 is in linear region,M100 will have a minimum current realized by the class ab circuit also. So, how to gurantee M110 and M111 have the same vgsteff in two different modes?
Q3---LMP91000 is a gas sensor interface chip, with its amplifier using this minimum selector class ab control circuit. Its static current consumption is about 2uA, and its max. current is +/-750uA.
Q4---I just want to know what the key factor to get a max. current output is in this structure. The ratios of M100/M101 to M110/M111 or other reasons?
Q5---Yes, the output transistors have to work in strong inversion mode.

I have done some theoretical derivations, if you are interested in them, please let me know, my email:Honey-a-ivy@hotmail.com. I really thank you for the discussions.

 

[erikl]

Q1---I am using transistors with their W<<L because of small current.

Do you want just a few nanoAmperes? The technology current (saturation current @ Inversion_Coefficient=IC=1 (moderate inversion) and W/L=1) for a 0.13µm process is ≈1µA, so with a W/L=0.13/10 you'll get ≈13nA. If you want even less, you could go into weak inversion operation, or you really have to serialize if L>10µm isn't allowed (this limitation concerns just analysis (in)accuracy, there are no physical or process limited restrictions on transistor lengths. Think of resistor lengths!). Moreover, your analysis result may be not too accurate for serial transistors, if you can't connect source to bulk (nmos in single well process).

Q2---There are some equations to calculate the max. current and min. current of the output stage. As the author said, M110 and M111 should have the same vgsteff (vgs-vth) in order to maintain the class ab signal at the gate of M2031. Right now, I found it difficult to realize this two transistors' vgsteff equal, because, there are two different operation regions of M115 during push and pull hardly. When M100 is pushing hardly, M115 is in saturation region, M101 will have a minimum current realized by the class ab control circuit. When M101 is pull hardly, M115 is in linear region,M100 will have a minimum current realized by the class ab circuit also. So, how to gurantee M110 and M111 have the same vgsteff in two different modes?

This isn't possible and not necessary: they only need the same vgsteff in quiescent state.

Q3---LMP91000 is a gas sensor interface chip, with its amplifier using this minimum selector class ab control circuit. Its static current consumption is about 2uA, and its max. current is +/-750uA.

Ok, thank you! I didn't find a dataSheet.

Q4---I just want to know what the key factor to get a max. current output is in this structure. The ratios of M100/M101 to M110/M111 or other reasons?

Yes, the ratios, and the source & drain connection resistances of the output transistors as low as possible by sufficient fingering.

 

[ivyahoney]

Do you want just a few nanoAmperes? The technology current (saturation current @ Inversion_Coefficient=IC=1 (moderate inversion) and W/L=1) for a 0.13µm process is ≈1µA, so with a W/L=0.13/10 you'll get ≈13nA. If you want even less, you could go into weak inversion operation, or you really have to serialize if L>10µm isn't allowed (this limitation concerns just analysis (in)accuracy, there are no physical or process limited restrictions on transistor lengths. Think of resistor lengths!). Moreover, your analysis result may be not too accurate for serial transistors, if you can't connect source to bulk (nmos in single well process).



This isn't possible and not necessary: they only need the same vgsteff in quiescent state.


Ok, thank you! I didn't find a dataSheet.



Yes, the ratios, and the source & drain connection resistances of the output transistors as low as possible by sufficient fingering.

Yes, I have given 10nA as a bias current, and I want to see if it works. I have increased the ratios of between M100/M101 and M110/M111 to 32.

I have followed your suggestion to set the vgsteff of both M110 and M111 equal.

In queiscent state, assuming the current through M112 is 10nA, M115, M113 and M110 have the same aspect ratio. M115 works in linear region, so current through M113 and M111 is twice of 10nA, which is about 20nA. The ids current through M101 is about 32 times of 20nA, which is about 640nA, and so does M100. By adding other branches including the input stages and the bias circuit, the overall consumption is less than 2uA.

I have attached the datasheet of LMP91000, please have a look.

I don't know how to keep the source-drain resistances of the output transistors as low as possible... :sad: As I mentioned before, I want this circuit to drive low load resistance (10~25 kilohms) and huge capacitance(100~200 millifarad). Because the current is so small, the source-drain resistance is inverse proportional to the source-drain current,isn't it?

I am not sure if you can understand my concerns. If not, I would like to explain more...

Thank you very much about your help!

 

[erikl]

In queiscent state, assuming the current through M112 is 10nA, M115, M113 and M110 have the same aspect ratio. M115 works in linear region, so current through M113 and M111 is twice of 10nA, which is about 20nA. The ids current through M101 is about 32 times of 20nA, which is about 640nA, and so does M100. By adding other branches including the input stages and the bias circuit, the overall consumption is less than 2uA.

Very good! A ratio of 32 isn't too much. I've already successfully used a ratio of 1000 (10mA/10µA).

I have attached the datasheet of LMP91000, please have a look.

Thank you!

I don't know how to keep the source-drain resistances of the output transistors as low as possible... :sad:

This was an advice for the layout: many single transistors ("fingers") in parallel reduces these resistances.

As I mentioned before, I want this circuit to drive low load resistance (10~25 kilohms) and huge capacitance(100~200 millifarad). Because the current is so small, the source-drain resistance is inverse proportional to the source-drain current,isn't it?

This is only valid when the output transistor operates in the linear ("triode") region, i.e. shortly before the required output voltage is reached. Before, it will work with constant current in the saturation region, so you better calculate the slew rate: e.g. 10^-6A/10^-1F = 10µV/s .

 

[ivyahoney]

Very good! A ratio of 32 isn't too much. I've already successfully used a ratio of 1000 (10mA/10µA).


Thank you!

This was an advice for the layout: many single transistors ("fingers") in parallel reduces these resistances.


This is only valid when the output transistor operates in the linear ("triode") region, i.e. shortly before the required output voltage is reached. Before, it will work with constant current in the saturation region, so you better calculate the slew rate: e.g. 10^-6A/10^-1F = 10µV/s .

You mean that you have successfully achieved the max. current of 10mA by only consuming 10uA static current? That is great!

What process do you use? 130nm process? As I mentioned before, I have used transistors which have long length because of low current bias, so how much bias current or total current consumption do you use?

When I am simulating this circuit, I used external common mode feedback to make the output voltage steady by using huge resistor and capacitor. The output voltage is keeped at half of power supply voltage, vdd/2. If I don't use the outside common voltage feedback, the output voltage will swing a lot due to the high gain of the first stage.

From the simulation results, it is evident the external feedback have keeped the common voltage of the output stage steady. But I want to see the inflences of the 'class ab control loop'.

As you know, there are two feedback loops, one is M111->M113->M115->M110->M112, the other one is M115->M110->M112. Changes on the gates of both M100 and M101 will go to the said two feedback loops and finnally get a set voltage at the gate(drain) of M112. How to simulate the 'class ab control loops' to see their infulences?

Can you share some specific results or your simulation methods with my? I think I missed some detailes perhaps. Thanks a lot for your sharing!

 

[erikl]

You mean that you have successfully achieved the max. current of 10mA by only consuming 10uA static current? That is great!

What process do you use? 130nm process? As I mentioned before, I have used transistors which have long length because of low current bias, so how much bias current or total current consumption do you use?

This was quite a different application (LDO) on a 180nm process. Total quiescent current consumption (no load) was ≈20µA , max. output current 15mA.

... Can you share some ... simulation methods with my?

Just use your normal application incl. feedback configuration (without the huge cap) and apply a slow triangle or sinus input.

 

[ivyahoney]

This was quite a different application (LDO) on a 180nm process. Total quiescent current consumption (no load) was ≈20µA , max. output current 15mA.


Just use your normal application incl. feedback configuration (without the huge cap) and apply a slow triangle or sinus input.

Ok, I will try again and find way out...Thanks!

By the way, what is your opinion on this class ab control structure, compared to the traditional trans-linear loop? I have found in papers saying that the minimum supply voltage is decreased to vgs+2*vdsat (2*vgs+2*vdsat for the traditional one). Are there any other benefits of this structure?

I am going to give a presentation later on, really need some solid provements. Please be kind to give some hints, like what else do you think should I take for considerations?

- - - Updated - - -

This was quite a different application (LDO) on a 180nm process. Total quiescent current consumption (no load) was ≈20µA , max. output current 15mA.


Just use your normal application incl. feedback configuration (without the huge cap) and apply a slow triangle or sinus input.

Ok, I will try again and find way out...Thanks!

By the way, what is your opinion on this class ab control structure, compared to the traditional trans-linear loop? I have found in papers saying that the minimum supply voltage is decreased to vgs+2*vdsat (2*vgs+2*vdsat for the traditional one). Are there any other benefits of this structure?

I am going to give a presentation later, really need some solid provements. Please be kind to give some hints, like what else do you think should I take for considerations?

 

[erikl]

I am going to give a presentation later, really need some solid provements. Please be kind to give some hints, like what else do you think should I take for considerations?

A disadvantage of this folded-mesh / minimum current selector class AB control structure is just its higher complexity, I think.

Did you check the lecture notes on Output Amplifiers which I linked to in my above post ("Here")?

You could also compare its output impedance and its frequency and phase behavior in comparison with the simpler Monticelli biasing scheme, see e.g. **broken link removed**.

 

[ivyahoney]

A disadvantage of this folded-mesh / minimum current selector class AB control structure is just its higher complexity, I think.

Did you check the lecture notes on Output Amplifiers which I linked to in my above post ("Here")?

You could also compare its output impedance and its frequency and phase behavior in comparison with the simpler Monticelli biasing scheme, see e.g. **broken link removed**.

Hi, erikl,

I have another question to ask, sorry to bother you.

Why the "minimum current" is needed for the class AB output stages? As the paper said, the minimum current of the inactive transistor is needed to prevent signal distortion (prevent the inactive transistor from cut off), another paper said, the distortion refers to the high-frequency distortion. So, what kind of the distortion?

I am confused about the requirement of the "minimum current" design, please be kind to help me out of this. Thanks a lot!

Ivy

 

[erikl]

... the minimum current of the inactive transistor is needed to prevent signal distortion (prevent the inactive transistor from cut off), another paper said, the distortion refers to the high-frequency distortion. So, what kind of the distortion?

I am confused about the requirement of the "minimum current" design

Without this minimum current guarantee, one of the prestages - at the limits of the large-signal operation range - could go to zero current and thus would force one of the output transistors also in its "off" mode, hence would change the output stage into a (half-wave) class-B or even class-C mode: Such modes of course have much larger distortion.

Distortion occurs at any frequency, it gets larger, however - given constant input level - with falling open-loop-gain, because the attenuation of the distortion (in first approximation) behaves like open-loop-gain/closed-loop-gain.

That's why distortion at higher frequencies (in the falling open-loop-gain range) always is larger - and so more important if in an considered (used) frequency range.