Waffle v/s Stripped Layout

[lastdance]

waffle transistor

For the layout of large power transistors,
what are the advantages/disadvantages of using stripped/waffle layout for MOS devices. Thanks

 

[Humungus]

waffle layout

A power device can have an equivalent W of several centimeters. As you cannot make a so long device you divide it into fingers. Also, you reduce the parasitic resistance in series with your transistor due to long access metal stripes.

 

[Colbhaidh]

waffle layouts

Waffle is typically used for high voltage discrete FETs (like 100V ++) which are vertical transistors.

 

[Teddy]

waffle transistors

Waffle makes more W per area. What I did not like on it was the fact of 1 contact / cell (sure depends how you make it). If this contact is not done well in process you are loosing quite a bit of W.

 

[hrkhari]

waffel drain

Hi Guys:

In context of high current draining transistor, typically in PA design, waffle layout technique would serve the purpose, the method of distributing the large transistor in sharing the drain and source in a tiled layout view utilized in waffle layout technique provides better current and thermal management effort. Hope this helps

Rgds

 

[LaughingMAN]

waffle layout of mos transistors

Hi All,

Where can I find an example of a waffle layout technique? Thanks.

 

[scottieman]

waffle layout design

Hi all,

As I known from my collegue, transistor in waffle sturcture, generally, cannot be recongized in LVS. Any one know how this problem can be solved?

Thanks
Scottie

 

[selvaraja]

technique of waffle layout

you need modify lvs script to make it wrk

 

[vijay.kumarreddy]

waffle layout in ic layout

in the waffel structure u cannot guarentee the width the of the edge fingers.this is the main disadvantage of the waffel structure