Video controller IP and PowerPC 405

[BlackOps]

powerpc 405 video

Hello! i have XUPV2P board, and i want to display video data from DDR SDRAM on PC VGA monitor with a C program running on PPC.

i already wrote and tested simple C program, which just fills the specified DDR Memory location with color information. now, i must make my video controller read it from DDR...and display appropriate data on VGA.

ok, i already have a VHDL code for video signal generation with 1024x768 60Hz. i tested it...it works. now.. i want to turn it to the Peripheral and add as IP to the EDK project. here is the top entity code for my controller:

ENTITY VGAcore IS PORT (

  SysClk:         IN STD_LOGIC;	-- 100 MHz system clock from AJ15 FPGA pin
  OutClk:			      OUT STD_LOGIC;	-- 65MHz 180 deg phase shifted clock for video chip

  hsync:         	OUT STD_LOGIC;	-- Horizontal synchronization signal for D-sub connector
  vsync:         	OUT STD_LOGIC;	-- Vertical synchronization signal for D-sub connector

  SYNC:         	 OUT STD_LOGIC;	-- !SYNC signal for the video chip
  BLANK:         	OUT STD_LOGIC;	-- !BLANK signal for the video chip

  Red_out:        OUT STD_LOGIC_VECTOR (7 DOWNTO 0);  -- 8 bit red color signal
  Green_out:      OUT STD_LOGIC_VECTOR (7 DOWNTO 0);  -- 8 bit green color signal	
  Blue_out:       OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- 8 bit blue color signal
  
    Red_in:        IN STD_LOGIC_VECTOR (7 DOWNTO 0);  -- 8 bit red color signal
    Green_in:      IN STD_LOGIC_VECTOR (7 DOWNTO 0);  -- 8 bit green color signal	
    Blue_in:       IN STD_LOGIC_VECTOR (7 DOWNTO 0); -- 8 bit blue color signal
    
Row_out: OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
Col_out: OUT STD_LOGIC_VECTOR(10 DOWNTO 0));

END VGAcore;

this entity will be used in the user_logic.vhd file, generated by the EDK Peripheral Wizard. Row_out and Col_out are signals coming from the internal state machine, which keeps track of the current pixel. (on which pixel the electron beam is at now..) it is considered that...in user_logic.vhd the logic receives those signals, compares them with another values of coordinates which come from PPC, and pass them back to VGAcore. VGAcore receives them as Blue_in..etc. and passes to the output...with Blue_out ports...

there is one thing... everyone suggests me to have some specified amount of SDRAM to store the entire screen page (as i did)
exactly: [1024x768x24] / 8 = 2.359296 bytes... but if so...then why do i need my VGAcore to keep track of the current pixel? why do i need Col_out and Row_out signals then? should i remove them?

and another question is... as i saw, every peripheral added to the EDK is assigned a driver... so, my video peripheral also will have a driver and run on PPC... but my idea is... i want to use PPC only to store video data inside SDRAM..nothing more!!

how to make my video peripheral standalone? running without drivers, and reading specified SDRAM locations automatically?

so i must use DMA to make my video peripheral read the DDR memory automatically and not to waste resources of PowerPC.
give a hint please, how to organize it? thanks!

if anyone did soemthing like this, please share ur experience, i'd appreciate it very much!

 

[ranggaperdana_06114]

powerpc 405

nice bro good & keep work...

 

[sajjadi335]

locallink powerpc 405

I just know that xilinx doesn't have any specific documents on generating peripherals using DMA (the PLBV46 migration document says you should see DMA migration chapter, which is non-existent). This is a problem I have too.
But I think for this to happen, in PLBV64 systems, you should design your core as an slave on the bus. PPC just controls control/status registers in the core (if any). Then, a LocalLink should be generated between your core and one of the ports of MPMC. Or you should use its SDMA link. I think the second is more logical, because PPC should know which part of the SDRAM you're accessing, so that no collision happens.

 

[karikalan_t79]

fpga powerpc std_logic

pix col and row is need in order to track which line is scan by sync generator, and keep alling with the sdram