dchan
Newbie level 3
Hi All,
I am a beginner to VHDL/Verilog coding and am trying to implement a feasible project.
I am considering 2 ideas:
1) Implementation of a Fully Associative or Set Associative Cache
2) Cache coherence in a 2-processor system
If you could please guide me on Verilog or VHDL coding references and which one of the above 2 would be a better topic to implement both from the learning and feasibility perspective it would be very helpful.
Thank you.
I am a beginner to VHDL/Verilog coding and am trying to implement a feasible project.
I am considering 2 ideas:
1) Implementation of a Fully Associative or Set Associative Cache
2) Cache coherence in a 2-processor system
If you could please guide me on Verilog or VHDL coding references and which one of the above 2 would be a better topic to implement both from the learning and feasibility perspective it would be very helpful.
Thank you.