jmoore
Newbie level 3
Hi
I have been trying to make a clean variable size memory bank with little to no success.
What i am trying to replace is the classic case statement :
process(clk_40,reset,wr,data,address)
begin
if clk_40'event and clk_40 = '1' then
if reset = '1' then
registers_int <= (others =>(others => '0'));
elsif wr = '1' then
case address is
when "00000000" => registers_int(0) <= data;
when "00000001" => registers_int(1) <= data;
....
with something that does not require adding new cases like this:
begin
out_regs <= registers_int;
process(clk,reset,wr,data,address)
begin
if clk'event and clk = '1' then
if reset = '1' then
registers_int <= (others =>(others => '0'));
elsif wr = '1' then
registers_int( conv_integer(address)) <= data;
end if;
end if;
I am getting the flowing error when I try and compile:
ERROR:HDLCompiler:432 - "/home/jmoore/devel/xilinx/hep015a_doric/arb_mem_bank.vhd" Line 57: Formal <arg> has no actual or default value.
INFO:HDLCompiler:1408 - "/build/xfndry10/O.61xd/rtf/vhdl/xst/src/syn_arit.vhd" Line 162. arg is declared here
INFO:HDLCompiler:1408 - "/build/xfndry10/O.61xd/rtf/vhdl/xst/src/syn_arit.vhd" Line 162. arg is declared here
ERROR:HDLCompiler:541 - "/home/jmoore/devel/xilinx/hep015a_doric/arb_mem_bank.vhd" Line 57: Type integer is not an array type and cannot be indexed.
I know this I probably a dead horse around here but any help would be appreciated.
I have been trying to make a clean variable size memory bank with little to no success.
What i am trying to replace is the classic case statement :
process(clk_40,reset,wr,data,address)
begin
if clk_40'event and clk_40 = '1' then
if reset = '1' then
registers_int <= (others =>(others => '0'));
elsif wr = '1' then
case address is
when "00000000" => registers_int(0) <= data;
when "00000001" => registers_int(1) <= data;
....
with something that does not require adding new cases like this:
begin
out_regs <= registers_int;
process(clk,reset,wr,data,address)
begin
if clk'event and clk = '1' then
if reset = '1' then
registers_int <= (others =>(others => '0'));
elsif wr = '1' then
registers_int( conv_integer(address)) <= data;
end if;
end if;
I am getting the flowing error when I try and compile:
ERROR:HDLCompiler:432 - "/home/jmoore/devel/xilinx/hep015a_doric/arb_mem_bank.vhd" Line 57: Formal <arg> has no actual or default value.
INFO:HDLCompiler:1408 - "/build/xfndry10/O.61xd/rtf/vhdl/xst/src/syn_arit.vhd" Line 162. arg is declared here
INFO:HDLCompiler:1408 - "/build/xfndry10/O.61xd/rtf/vhdl/xst/src/syn_arit.vhd" Line 162. arg is declared here
ERROR:HDLCompiler:541 - "/home/jmoore/devel/xilinx/hep015a_doric/arb_mem_bank.vhd" Line 57: Type integer is not an array type and cannot be indexed.
I know this I probably a dead horse around here but any help would be appreciated.