VHDL synthesizable D-flop flop

[Pradeepa_kck]

Following is a working VHDL code for a D-flip flop with Asynchronous reset. Note that it is using a variable state for it's operation.

architecture var of D_FF is
begin
p0: process(Clock, Reset) is
variable state : std_logic;
begin
if(Reset = '0') then
state := '0';
elsif rising_edge(Clock) then
state := D;
end if;
Q <= state;
Qbar <= notstate;
end process p0;
end architecture var;

My problem is that without using this state variable can't we simply drive the output by D. Then we will not need a variable to store the state.

Q <= D;
Q <= not D;

Is there any drawback of doing that?

 

[TrickyDicky]

no. The standard template does not use variables. Abd 99% off synthesisable code does not need variables.

 

[embeddedlover]

@trickydicky..

Just intruding into pradeepa thread..

1. Irrespective of using variable logic as pradeepa mentioned here or a standard template, the synthesis will lead to same schematic at the output.. am i right?
2. But the space EEPROM occupied by program and execution time are high in this logic than standard one.. am i right?

 

[FvM]

The standard VHDL template would use a signal instead of a variable. But the synthesized logic would usually be the same if you use a variable.

2. But the space EEPROM occupied by program and execution time are high in this logic than standard one.. am i right?

You are talking about what? Where do you see an EEPROM involved with the problem?