Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

vhdl syntax problem

Status
Not open for further replies.

rourabpaul

Member level 3
Joined
Aug 14, 2010
Messages
67
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Location
kolkata
Activity points
1,747
i have a signal 'S' of n bits in vhdl , and n is any positive value defined in a generic,
say in that case n=8,
i write
if n="11111111" then
(some data)
end if;

but when i change the generic value(n) then i have to manipulate the if condition also,i dnt want to do it, i only want to change the value of n,
what will be my syntax in the 'if' condition
 

if u change the n ..its value automatically change...or u can define n and its value in generic...or chk in if statement n is true or false
 

if S = (S'range => '1') then

I'm assuming the example used S, as n = "11111111" isn't valid if n is an integer.
 
  • Like
Reactions: FvM

    FvM

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top