vhdl syntax help needed

[sarah23]

vhdl:
Add_next:hybadd port map(PC_out,(2 => '1',others => '0'),add_next_out);

verilog converted:
hybadd Add_next (PC_out, {2 : 1'b1, {a{1'b0}}}, add_next_out);

i don't understand wat does this means

(2 => '1',others => '0') <==> {2 : 1'b1, {a{1'b0}}}

 

[TrickyDicky]

it sets bit 2 to '1' and all other bits to '0'.
so if it is a bus declared (7 downto 0), it would set the value to "00000100".