Richard Keno Garvey
Newbie level 3
hello guys i would like you guys to help me i am have an assignment. i have to design and implement a Simple Calculator (addition and subtraction)... (multiplication and division would be great also) in VHDL and simulate the operations of this system on a board. please guys help me. i have most addition and subtraction of working as long as the numbers are positive, which is the problem i also need negative numbers. i havent done division and multiplication because if time constraints if you could help with that i would be very greatful
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; ENTITY midterm0 IS PORT ( Num1: IN STD_LOGIC_VECTOR(3 DOWNTO 0); Num2: IN STD_LOGIC_VECTOR(3 DOWNTO 0); key: IN STD_LOGIC_VECTOR(2 DOWNTO 0); result: out std_logic_vector(3 downto 0); GPIO_0: OUT STD_LOGIC; GPIO_1: OUT STD_LOGIC); END midterm0; ARCHITECTURE behavior OF midterm0 IS BEGIN process(num1,num2) begin if (key(0) = '0') then result <= (Num1)+(Num2); elsif key(1) = '0' then result <= (Num2)-(Num1); end if; GPIO_0 <= key(0); GPIO_1 <= key(1); END process; end behavior;
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; ENTITY midterm1 IS PORT (result :IN std_logic_vector(3 downto 0); resultout :OUT std_logic_vector (6 downto 0) ); END midterm1; ARCHITECTURE behavior OF midterm1 IS Begin resultout <= "1000000" when result="0000" else "1111001" when result="0001" else "0100100" when result="0010" else "0110000" when result="0011" else "0011001" when result="0100" else "0010010" when result="0101" else "0000010" when result="0110" else "1111000" when result="0111" else "0000000" when result="1000" else "0010000" when result="1001" else "1000000" when result="1010" else "1111001" when result="1011" else "0100100" when result="1100" else "0110000" when result="1101" else "0011001" when result="1110" else "1000000"; END behavior;
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; ENTITY midterm2 IS PORT (result :IN std_logic_vector(3 downto 0); resultout1 :OUT std_logic_vector (6 downto 0) ); END midterm2; ARCHITECTURE behavior OF midterm2 IS Begin resultout1 <= "1000000" when result="0000" else "1000000" when result="0001" else "1000000" when result="0010" else "1000000" when result="0011" else "1000000" when result="0100" else "1000000" when result="0101" else "1000000" when result="0110" else "1000000" when result="0111" else "1000000" when result="1000" else "1000000" when result="1001" else "1111001" when result="1010" else "1111001" when result="1011" else "1111001" when result="1100" else "1111001" when result="1101" else "1111001" when result="1110" else "1000000"; END behavior;
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; ENTITY midterm3 IS PORT (num1 :IN std_logic_vector(3 downto 0); resultnum1 :OUT std_logic_vector (6 downto 0) ); END midterm3; ARCHITECTURE behavior OF midterm3 IS Begin resultnum1 <= "1000000" when num1="0000" else "1111001" when num1="0001" else "0100100" when num1="0010" else "0110000" when num1="0011" else "0011001" when num1="0100" else "0010010" when num1="0101" else "0000010" when num1="0110" else "1111000" when num1="0111" else "0000000" when num1="1000" else "1000000"; END behavior;
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; ENTITY midterm4 IS PORT (num2 :IN std_logic_vector(3 downto 0); resultnum2 :OUT std_logic_vector (6 downto 0) ); END midterm4; ARCHITECTURE behavior OF midterm4 IS Begin resultnum2 <= "1000000" when num2="0000" else "1111001" when num2="0001" else "0100100" when num2="0010" else "0110000" when num2="0011" else "0011001" when num2="0100" else "0010010" when num2="0101" else "0000010" when num2="0110" else "1111000" when num2="0111" else "0000000" when num2="1000" else "1000000"; END behavior;