VHDL Signed math Overflow equality

[dareon]

I am trying to make an integrator using signed math and I don't want to it to overflow.

INTEGRATOR: process (CLK1MHZ, IG, ERROR)
variable INTGT : signed(5 downto 0);
begin
if rising_edge(CLK1MHZ) then
INTGT := INTG + ERROR*IG;

if INTGT > "00100" then
INTG <= "00111";
elsif INTGT < "11000" then
INTG <= "11000";
else
INTG <= INTGT;
end if;
end if;
end process;

Whenever I do this comparison ISE gives me
INFO:Xst:2261 - The FF/Latch <INTG_4> in Unit <NANOPOSITIONER> is equivalent to the following 2 FFs/Latches, which will be removed : <INTG_5> <PIDO_5>


While I understand why I get this info. The higher order bits will always be the same because of the limit. What I want to make sure of is that the limits on my integrator are calculated on what the actual addition would be or will there be and overflow and the equality be calculated on it?

Thank You