VHDL - serial to parralel shift register with a twist.

[Pheetuz]

Hi folks.

Got a project that I am working on atm, where i have to take in a number in parallel and convert / send it via a link in serial format and then convert this data stream back into parallel to be outputted on a seven segment display.

I have written the transmitter code with little problem but am having a few issues with the reciever.

The trasnsmitter attaches the code "1011" to the original data before sending it (on the right hand side of the original data)... This is my identification code that i will use to tell the reciever when the data has been shifted the correct number of times.

I have an internal file called temp that i am using as a shift register and only want temp to be copied to the output when "1011" is in temp(3 downto 0).

On top of this, I only want temp to be copied to the ouput if temp(5) is a logic '0' (when temp(3 downto 0) = "1011") otherwise i want another code to be copied to the output -- exaclty what code this will be is unknow at present.

Below is some code that i have written, it will not assemble at present and im in the process of sorting that out lol, but any feedback would be appreciated.



library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity Shift_reg is port (
reset, clk, bin: in std_logic;
pout: out std_logic_vector (3 downto 0));

end Shift_reg;


architecture reg of Shift_reg is

begin
Right: process (clk, bin, reset)
variable temp : std_logic_vector (7 downto 0);
variable temp1 : std_logic_vector (7 downto 0);
variable temperror : std_logic_vector (3 downto 0);
begin

--temperror := "0110"

if rising_edge(clk) then

temp := temp srl 1;
temp(7) := bin;


else

if temp(3 downto 0) = "1011" then

if temp(5) = '0' then
pout(3 downto 0) <= temp(7 downto 4);
temp := temp srl 1;



elsif temp(5) = '1' then
pout <= temperror(3 downto 0);

end if;


end if;

end if;



-- [If bit 5 = 1 then pout <= ERROR];


end process;
end reg;

Many thanks.

/Pete

 

[vipinlal]

if rising_edge(clk) then 

temp := temp srl 1; 
temp(7)	:= bin; 


else 

if	temp(3 downto 0) = "1011" then	

if temp(5) = '0' then	
pout(3 downto 0)	<=	temp(7 downto 4); 
temp := temp srl 1;

In your code, you are writing to temp at the Rising edge of the clock.At the same time in the else statement you have a "temp := temp srl 1" statement.This means you are trying to write to temp at both the clock edges.I dont think that is synthesisable.

--vipin
https://vhdlguru.blogspot.com/

 

[Pheetuz]

Thanks Vipin.

I have just re-written the code to try to make it clearer and have come up with this, is it possible to use a statement such as

if temp(3 downto 0) and rotate = '0' then .... ??

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity Shift_reg is port (
	reset, clk, bin:	in std_logic;
	pout:	out	unsigned(3 downto 0));

end Shift_reg;


architecture reg of Shift_reg is

begin
	Right:	process (clk, bin, reset)
		variable temp : unsigned (7 downto 0);
		variable temp1 : unsigned (7 downto 0);
		variable error : unsigned (3 downto 0);
		variable rotate	: std_logic;	
		begin


			if 	rising_edge(clk) then

				temp := temp ror 1;  
				temp(7)	:= bin;
				rotate	:= '1';
				error	:= "0110";

			
						if temp(3 downto 0) -- and rotate = '0' then

								if	temp(5) = '1' then
								pout <= error;

								else
								pout <= temp(7 downto 4);
								rotate := '1';

								end if;

						end if;


			  end if;


	end process;
	end reg;

Many thanks.

/Pete

 

[vipinlal]

The second code will not have any problem with respect to synthesis.But you have to simulate it and see whether it is working in the way you want.

--vipin
https://vhdlguru.blogspot.com/