vhdl programming with xilinx ISE and encountring errors, can anyone help me

[ranjbar_7]

hi

i have wriiten this simple vhdl code and i expect no error but i get this erros and i don't know why
would u please help me


thanks in advansce
code
-----------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;



entity project1 is
Port ( data_in : in STD_LOGIC_VECTOR (0 downto 32);
output : out STD_LOGIC_VECTOR (0 downto 31);
hit : out std_logic

);
end project1;
-------------------------------------------------------------------
architecture Behavioral of project1 is
type ram_array is array (0 to 32 ) of std_logic_vector(31 downto 0);


CONSTANT tag_array : ram_array :=(x"0000",x"1000",x"0001",x"0002",x"0004",x"00005",x"0006",x"0007",
x"0008",x"0009",x"000A",x"000B",x"000C",x"000D",x"000E",x"000F",
x"010",x"0020",x"0030",x"0040",x"0050",x"0060",x"0070",x"0080",
x"0090",x"00A0",x"00B0",x"00C0",x"00D0",x"00E0",x"00F0",x"0100");

CONSTANT data_array: ram_array:=(x"00aAB",x"0AD0",x"0ABC",x"ABC0",x"ABCD",x"BCDE",x"BCDF",x"DFFF",
x"AAAA",x"BBBB",x"CCCC",x"DDDD",x"EEEE",x"FFFF",x"ABAB",x"ACAC",
x"ADAD",x"AFAF",x"AEAE",x"ABBB",x"ACCC",x"AFFF",x"ADDD",x"BAAA",
x"BABA",x"CACA",x"DADA",x"EAEA",x"FAFA",x"00AD",x"00AF",x"00CF");


begin

for i in 0 to 32 LOOP

if ( data_in=data_array(i)) THEN

hit <= '1';
output <= tag_array (i); else

hit<='0';
output<= data_in ;


end if;
end loop;




end Behavioral;



-------
erros
ERROR:HDLCompiler:806 - "C:\Documents and Settings\project\project1.vhd" Line 54: Syntax error near "for".
ERROR:HDLCompiler:806 - "C:\Documents and Settings\project\project1.vhd" Line 56: Syntax error near "THEN".
ERROR:HDLCompiler:69 - "C:\Documents and Settings\project\project1.vhd" Line 59: <i> is not declared.
ERROR:HDLCompiler:806 - "C:\Documents and Settings\project\project1.vhd" Line 59: Syntax error near "else".
ERROR:HDLCompiler:806 - "C:\Documents and Settings\project\project1.vhd" Line 65: Syntax error near "if".
ERROR:HDLCompiler:854 - "C:\Documents and Settings\project\project1.vhd" Line 37: Unit <behavioral> ignored due to previous errors.

 

[barry]

There are no line numbers in your listing, which makes it a little difficult, but here are a few comments:

1) Don't use IEEE.std_logic_arith.all, use ieee.numeric.std instead
2) (0 downto 32) is wrong, what you mean is (32 downto 0) (or maybe (0 to 32)

But your main problem is that the for-loop has to be inside a process.

 

[ranjbar_7]

thank you barry