VHDL: 'open' ports assignment

[Taher_Selim]

Hello,
I had a component in my VHDL design. some ports of this component are not needed to be connected. I have used 'open' in port map section. This works ok for ports of mode out. for ports of mode in, I have to set initial value for the port first. As an example

Component  HalfAdder 
Port (
Clk : in std_logic;
Rst: in std_logic;
In_1:  in std_logic;
In_2: in std_logic := ‘1’ ;
Carry: out std_logic;
Sum : out std_logic
);
End component;

ModifiedAdder:  HalfAdder 
Port map (
Clk => clk,
Rst => rst,
In_1  =>  In_1,
In_2  => open,
Carry  => open,
Sum  => sum
);

My question, Why I have to initialize the input ports. i.e why I can't leave it open without assigning initial value?

 

[dpaul]

Input ports cannot be left unconnected according to the IEEE specification. All inputs must be driven.
If you are not assigning any value to the inputs it will lead to error value propagation in the design.

 

[Taher_Selim]

I will be grateful if you post here this part of the IEEE specification that mention this point as I don't have the standard right now.

 

[FvM]

In previous VHDL-2000 you find this clear statement.

1.1.1.2 Ports
(...)
A port of mode in may be unconnected or unassociated only if its declaration includes a default expression.

 

[sherif123]

As said in the standard, you can set default value in the entity declaration like

input_data : in std_logic_vector(7 downto 0):= "00000000";

If you left that port (input_data) open, no error will be reported. You do this in the component declaration on the parent design block.